US-CA-San Jose Sr. VLSI Chip Implementation Engineer

[Daniel Parrillo]

Our
clien
's patented architecture dramatically reduces power and
cost
f video compression ICs. Supporting H.264, WM9, MPEG2 and
MPE
4, and leverages it’s patented architecture to support
multip
e standards without sacrificing power or price.

Ideal candidate will be experienced with video compression
I
s, H.264, MPEG 2-4, etc... and the client is ONLY
interested
n "ideal candidates" !!!

The Senior VLSI Chip Implementation Engineer is
responsible
or the following:

* Finalizing the technical evaluation of candidate silicon
v
ndors
* Being the liason to the backend contractor and ensuring
su
cess on all phases of silicon implementation:
floorplanning;
lock, reset, scan routing; power distribution; block place
&
oute; parasitic extraction, timing analysis; physical
verific
tion (DRC, LVS, formal equivalence checking).
* Designing the actual physical implementation of our
low-po
er architecture, which affects clock and power domains;
power
estimation
* Evaluating, selecting, & integrating all analog IP:
DACs,
LLs, DLLs
* Designing the physical interface for DDR-DRAM (selecting
D
L, pads, latches, clocking scheme, performing timing
analysis

* Selecting the chip package & determining the final chip
pi
out
* Determining the chip floorplan & working on it with
backen
vendor
* Preparing chip top-level netlist: integrating digital
bloc
s, preparing RAM macro front-end views, integrating chip IO
p
ds, models of analog cells, working with DFT engineer on
test
debug requirements (scan chain, RAM BIST collars, etc.)
* Participating in the lab bringup of first-silicon ASICs

Requirements
============
MSEE with at least 7 years experience in the silicon
impleme
tation areas listed above as responsibilities of this
positio

Demonstrated success delivering working silicon for a
variet
of products
Experience with EDA floorplanning, clock-tree synthesis,
pla
e & route, extraction, and timing analysis & simulation
tools

Experience writing code in Verilog and using Verilog
simulat
rs and synthesis tools
Proficiency in Tcl and common UNIX scripting languages
(perl
csh, sh)
Extensive experience using the PrimeTime static timing
analy
is tool
Experience in the bringup & debug in the lab of
first-silico

Knowledge of low-power design techniques a plus

For IMMEDIATE consideration, please forward a copy of your
d
tailed, chronological resume (in MS word or .RTF format) to:

Daniel Parrillo
President
Strategi LLC
Phone #: 415-519-1828
E-mail:

PLEASE - NO THIRD PARTY VENDORS, AGENCIES OR CONSULTING
FIRM
!!!

PLEASE - ONLY APPLY IF YOU QUALIFY AND HAVE THE EXPERIENCE
W
TH VIDEO COMPRESSION, H.264, MPEG 2-4, ETC.

Requirements:

Ideal candidate will be experienced with video compression
I
s, H.264, MPEG 2-4, etc... and the client is ONLY
interested
n "ideal candidates" !!!

MSEE degree, 7 years silcon implementation exp
EDA floorplanning, clock-tree synthesis, place & route,
extr
ction, timing analysis and simulation tools exp.
Verilog code and simulation tools
Extensive exp with PrimeTime Static timing tool

Additional Information:

Job Number: JN-VLSI-SR
Position Type: Full Time

Contact Information:

Email: int...@postmyjobs.com

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