Q. re BEVENT

[Steven Hirsch]

I just received a "new" KDJ11-A CPU and am putting it through its paces
with a QBone as the only other board present. The XXDP test monitor comes
up without difficulty and all CPU board tests pass except for the BEVENT
suite. It trips at the first one (code 01166). If I set the test
configuration register to skip BEVENT it passes.

The DEC test source and M8192 manual disagree on which jumper disables
halt trap, but I've tried it both ways and nothing changes.

From what I gather in the test sources, the QBone LTC provides a
line-frequency interrupt that the test relies upon. I do have an 'en
kw11' line in the .cmd file, but am I also supposed to configure this
device (beyond a simple enable)? The Heath H11 power supply can generate
LTC, but I have it disabled.

Any advice appreciated.

Steve


--

[Jay Jaeger]

The Unibone does NOT provide a 60 Hz LTC signal to the backplane without adding some circuitry.  I would guess that the QBone would be the same.  I wired up a little 555 circuit to provide it.  I think if you search in this forum for "LTC" and "555" you will probably find a reference to the circuit.

Or if, as you note, the H11 power supply can provide the LTC signal to the backplane that would be the easiest, and probably best way to go.

JRJ

[Steven Hirsch]

On Sat, 26 Nov 2022, Jay Jaeger wrote:

> The Unibone does NOT provide a 60 Hz LTC signal to the backplane without
> adding some circuitry.  I would guess that the QBone would be the same. 
> I wired up a little 555 circuit to provide it.  I think if you search in
> this forum for "LTC" and "555" you will probably find a reference to the
> circuit. Or if, as you note, the H11 power supply can provide the LTC
> signal to the backplane that would be the easiest, and probably best way
> to go.

I *knew* I was missing something basic. Thanks for the clarification.
For some reason I had it in my head that the 'kw11' device provided
interrupts.

>
> JRJ
>
> On Saturday, November 26, 2022 at 4:05:19 PM UTC-6 snhi...@gmail.com wrote:
> I just received a "new" KDJ11-A CPU and am putting it through its paces
> with a QBone as the only other board present. The XXDP test monitor comes
> up without difficulty and all CPU board tests pass except for the BEVENT
> suite. It trips at the first one (code 01166). If I set the test
> configuration register to skip BEVENT it passes.
>
> The DEC test source and M8192 manual disagree on which jumper disables
> halt trap, but I've tried it both ways and nothing changes.
>
> From what I gather in the test sources, the QBone LTC provides a
> line-frequency interrupt that the test relies upon. I do have an 'en
> kw11' line in the .cmd file, but am I also supposed to configure this
> device (beyond a simple enable)? The Heath H11 power supply can generate
> LTC, but I have it disabled.
>
> Any advice appreciated.
>
> Steve
>
>
> --
>

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--

[Steven Hirsch]

On Sat, 26 Nov 2022, Jay Jaeger wrote:

> Or if, as you note, the H11 power supply can provide the LTC
> signal to the backplane that would be the easiest, and probably best way
> to go.

I enabled LTC on the power supply and verified a 60 hz. clock at the
BEVENT line to the backplane. The test is still failing.

I suppose it's possible the BEVENT hardware is broken, but I still think
there's something I'm misconfiguring - probably the CPU board jumpers.



--

[Joerg Hoppe]

Hi Steven, Jay,

> The Unibone does NOT provide a 60 Hz LTC signal to the backplane without
> adding some circuitry. I would guess that the QBone would be the same. I
> wired up a little 555 circuit to provide it. I think if you search in this
> forum for "LTC" and "555" you will probably find a reference to the circuit.

UniBone and QBone differ here:
UniBone produces no LTC, but surely will in the next hardware (still
learning!)

QBone produces a 50Hz signal which can be routed to backplane BEVENT via
a jumper.

See

http://retrocmp.com/projects/qbone/314-qbone-installation

for lengthy discussion about use of BEVENT.

kind regards,

Joerg

[Steven Hirsch]

On Sun, 27 Nov 2022, Joerg Hoppe wrote:

> Hi Steven, Jay,
>> The Unibone does NOT provide a 60 Hz LTC signal to the backplane without
>> adding some circuitry. I would guess that the QBone would be the same. I
>> wired up a little 555 circuit to provide it. I think if you search in this
>> forum for "LTC" and "555" you will probably find a reference to the
>> circuit.
>
> UniBone and QBone differ here:
> UniBone produces no LTC, but surely will in the next hardware (still
> learning!)
>
> QBone produces a 50Hz signal which can be routed to backplane BEVENT via a
> jumper.
>
> See
>
> http://retrocmp.com/projects/qbone/314-qbone-installation
>
> for lengthy discussion about use of BEVENT.

Thanks for the link - don't know how I missed that. At any rate, I ended
up configuring the Heath power supply to generate 60 Hz BEVENT and
verified that it appeared on the bus.

Still, the BEVENT tests fail immediately with code 01166. I have tried a
lot of CPU board jumper settings with no change in behavior. Before I
assume the CPU is defective, I'd really appreciate confirmation that a
BEVENT test succeeds for another M8192 owner. Also would like a review of
the proper CPU jumpering for this test. The test sources and M8192 docs
disagree on the location of the trap-disable jumpers.

There may well be a problem with BEVENT, since 2.11 BSD hangs at boot as
do some of the RSX-11 systems. I'm hoping the BEVENT register is external
to the large ceramic CPU chip.

>
> kind regards,
>
> Joerg
>
>
>>
>> Or if, as you note, the H11 power supply can provide the LTC signal to the
>> backplane that would be the easiest, and probably best way to go.
>>
>> JRJ
>>
>> On Saturday, November 26, 2022 at 4:05:19 PM UTC-6 snhi...@gmail.com wrote:
>>
>>> I just received a "new" KDJ11-A CPU and am putting it through its paces
>>> with a QBone as the only other board present. The XXDP test monitor comes
>>> up without difficulty and all CPU board tests pass except for the BEVENT
>>> suite. It trips at the first one (code 01166). If I set the test
>>> configuration register to skip BEVENT it passes.
>>>
>>> The DEC test source and M8192 manual disagree on which jumper disables
>>> halt trap, but I've tried it both ways and nothing changes.
>>>
>>> From what I gather in the test sources, the QBone LTC provides a
>>> line-frequency interrupt that the test relies upon. I do have an 'en
>>> kw11' line in the .cmd file, but am I also supposed to configure this
>>> device (beyond a simple enable)? The Heath H11 power supply can generate
>>> LTC, but I have it disabled.
>>>
>>> Any advice appreciated.
>>>
>>> Steve
>>>
>>>
>>> --
>>>
>

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--

[Mark Matlock]

Steve,
I have a M8192 CPU that I could put in my MINC that has a QBone. What is the BEVENT diagnostic test that you want to have checked on another M8192. I can probably check mine this afternoon.

By the way, RSX-11 runs in a unusual way without the LTC. It will boot but once the RSX executive finishes all the work that it has in the queue it executes a WAIT instruction. The only way to wake it up is with an interrupt which normally comes from the LTC, but can also come from other peripherals such as a DLV11. So you can get RSX to limp (perhaps more crawl) along by typing characters on a serial port where it is checking to see if someone is wanting to long in and while it is awake it executes anything else that needs to be done. This was behavior often seen on the BA11 box with a LTC switch in the wrong position.

Best,
Mark

> To view this discussion on the web visit https://groups.google.com/d/msgid/unibone/6c7fde1-d844-e37-b77d-a480f7a543b9%40fast.net.

[Steven Hirsch]

On Sun, 27 Nov 2022, Mark Matlock wrote:

> Steve,

> I have a M8192 CPU that I could put in my MINC that has a QBone. What
> is the BEVENT diagnostic test that you want to have checked on another
> M8192. I can probably check mine this afternoon.

Hi, Mark.

Try running ZKDJB2 with the default configuration flags (0). For me, it
fails immediately with code 01166 (the first in a series of BEVENT
handling tests).

> By the way, RSX-11 runs in a unusual way without the LTC. It will boot
> but once the RSX executive finishes all the work that it has in the
> queue it executes a WAIT instruction. The only way to wake it up is with
> an interrupt which normally comes from the LTC, but can also come from
> other peripherals such as a DLV11. So you can get RSX to limp (perhaps
> more crawl) along by typing characters on a serial port where it is
> checking to see if someone is wanting to long in and while it is awake
> it executes anything else that needs to be done. This was behavior often
> seen on the BA11 box with a LTC switch in the wrong position.

Ok, that's more support for my theory about BEVENT not being handled! If
I boot 2.11 BSD Unix from Joerg's QBone "application" it hangs
periodically. If I type anything at the console it shows a flurry of
activity on the QProbe before going quiescent. Further typing triggers
another brief burst of activity, etc.

Would appreciate it if you could check your CPU in an equivalent setup
(CPU + QBone only). In the interim, I'm going to spend some quality time
with the M8192 schematic and see if I can do some deep troubleshooting.

I *think* the BEVENT register is a TTL latch on the board rather than
being embedded in the CPU chip itself. We'll see.

Thanks for the reply!

--

[Steven Hirsch]

<big sigh...>

Note to self: Next time I'm convinced that a signal is "present on the
bus" this should be verified at every applicable connector. Turns out
that while BEVENT was connected through vertically on the backplane
between the four B and four D connectors, never the twain shall meet.
There was continuity from the power supply BEVENT only to the B
connectors and, indeed, the PCB layout and x-ray pictorial show no
evidence of a trace between the sets. I added a jumper to bring the D
connectors into the fold and - bingo - everything is working correctly.

2.11 BSD boots and the ZKDJB2 CPU test now passes.

At the time my original H-11 (not the 'A' model) was sold they were using
the quad-height M7264 LSI-11/03 CPU exclusively. I'm betting that it
picked up BEVENT from the 'B' connectors. I'll further wager that the D
connectors will show continuity on an H-11A backplane (which definitely
has a different part number).

Thanks to all who provided valuable input! This was a great learning
experience.

Steve


--

[Mark Matlock]

Steve,
I’m glad to hear that the fix was not difficult once you figured out what was going on.

Best,
Mark

[Steven Hirsch]

On Sun, 27 Nov 2022, Mark Matlock wrote:

> Steve,
> I’m glad to hear that the fix was not difficult once you figured out what was going on.

You and me both. The Heath backplane has a bunch of oddities. To
summarize the ones I know about:

Board orientation is flipped as compared to DEC card cages. Component
side faces down.

BEVENT signals are strapped vertically on column B and D, but the latter
set is floating and not wired to power supply BEVENT - only B is.

BA18 - BA21 are not bussed.

Heath uses AH1 on column C for SRUN signal. 11/73 CPUs generate SRUN on
AF1. I bussed AH1 and AF1 together on columns A and C for more flexibility
in installing a dual-height CPU.

There may be more, but these are the ones I've had to correct so far.

--