Results from Unibone latch tests with an M9302 terminator with active SACK logic

[klapperp]

During our adventure with a PDP-11/60, we decided to build a Unibone to have measurement technology available for the Unibus. That worked out well, and in the meantime, we have fully assembled 2 Unibus boards and started testing them.

The offline tests were successful right away, and we were also able to finally complete the tests of the "latches" with the help of a DD11-DK backplane. However, we noticed something that didn’t seem entirely logical to us.

At first, we had equipped our backplane with an M9302 terminator with active SACK logic and successfully carried out the SACK turnaround test.

TL>>>gst

Test SACK turnaround of M9302 terminator.
GRANT lines BG4,BG5,BG6,BG7,NPG are stimulated randomly,
if at least one is active, SACK must be asserted by M9302 terminator.
Starting now, stop with ^C ...
^CTest stopped by user after 1036189 operations.

0) buslatch[0] = 0x00 (bits = 0x1f, R/W bits = 0x1f)
1) buslatch[1] = 0x01 (bits = 0x7f, R/W bits = 0x7f)
2) buslatch[2] = 0x00 (bits = 0xff)
3) buslatch[3] = 0x00 (bits = 0xff)
4) buslatch[4] = 0x00 (bits = 0x3f, R/W bits = 0x3f)
5) buslatch[5] = 0x00 (bits = 0xff)
6) buslatch[6] = 0x00 (bits = 0xff)
7) buslatch[7] = 0x00 (bits = 0x3f, R/W bits = 0x3f)

TL>>>

Then the following sequence:

TL>>>1 o

Highspeed "moving ones" in register latch 1, stop with ^C.
^C
1461302 tests successful.
0) buslatch[0] = 0x00 (bits = 0x1f, R/W bits = 0x1f)
1) buslatch[1] = 0x04 (bits = 0x7f, R/W bits = 0x7f)
2) buslatch[2] = 0x00 (bits = 0xff)
3) buslatch[3] = 0x00 (bits = 0xff)
4) buslatch[4] = 0x00 (bits = 0x3f, R/W bits = 0x3f)
5) buslatch[5] = 0x00 (bits = 0xff)
6) buslatch[6] = 0x00 (bits = 0xff)
7) buslatch[7] = 0x00 (bits = 0x3f, R/W bits = 0x3f)

TL>>>0 o

Highspeed "moving ones" in register latch 0, stop with ^C.
^C
361975 tests successful.
0) buslatch[0] = 0x0f (bits = 0x1f, R/W bits = 0x1f)
1) buslatch[1] = 0x24 (bits = 0x7f, R/W bits = 0x7f)
2) buslatch[2] = 0x00 (bits = 0xff)
3) buslatch[3] = 0x00 (bits = 0xff)
4) buslatch[4] = 0x00 (bits = 0x3f, R/W bits = 0x3f)
5) buslatch[5] = 0x00 (bits = 0xff)
6) buslatch[6] = 0x00 (bits = 0xff)
7) buslatch[7] = 0x00 (bits = 0x3f, R/W bits = 0x3f)

TL>>>1 o <== HERE IS AN ERROR

Highspeed "moving ones" in register latch 1, stop with ^C.
pass 0 test_register_simple_pattern(2, 1): wrote 0x1, read 0x21
Signal path for bus latch 1, bit 5 (mask 0x20):
  Write: P9.27 -> J10.6 DATOUT_5 -> U30.14 -> U30.15 -> U32.11 -> U32.12 -> SACK
  Read : P8.42 <- J17.6 DATIN_5 <- U29.13 <- U29.07 <- U32.10 <- U32.12 <- SACK
0) buslatch[0] = 0x0f (bits = 0x1f, R/W bits = 0x1f)
1) buslatch[1] = 0x21 (bits = 0x7f, R/W bits = 0x7f)
2) buslatch[2] = 0x00 (bits = 0xff)
3) buslatch[3] = 0x00 (bits = 0xff)
4) buslatch[4] = 0x00 (bits = 0x3f, R/W bits = 0x3f)
5) buslatch[5] = 0x00 (bits = 0xff)
6) buslatch[6] = 0x00 (bits = 0xff)
7) buslatch[7] = 0x00 (bits = 0x3f, R/W bits = 0x3f)

TL>>>gst

Test SACK turnaround of M9302 terminator.
GRANT lines BG4,BG5,BG6,BG7,NPG are stimulated randomly,
if at least one is active, SACK must be asserted by M9302 terminator.
Starting now, stop with ^C ...
^CTest stopped by user after 555030 operations.

0) buslatch[0] = 0x00 (bits = 0x1f, R/W bits = 0x1f)
1) buslatch[1] = 0x01 (bits = 0x7f, R/W bits = 0x7f)
2) buslatch[2] = 0x00 (bits = 0xff)
3) buslatch[3] = 0x00 (bits = 0xff)
4) buslatch[4] = 0x00 (bits = 0x3f, R/W bits = 0x3f)
5) buslatch[5] = 0x00 (bits = 0xff)
6) buslatch[6] = 0x00 (bits = 0xff)
7) buslatch[7] = 0x00 (bits = 0x3f, R/W bits = 0x3f)

TL>>>1 o

Highspeed "moving ones" in register latch 1, stop with ^C.
^C
897873 tests successful.
0) buslatch[0] = 0x00 (bits = 0x1f, R/W bits = 0x1f)
1) buslatch[1] = 0x08 (bits = 0x7f, R/W bits = 0x7f)
2) buslatch[2] = 0x00 (bits = 0xff)
3) buslatch[3] = 0x00 (bits = 0xff)
4) buslatch[4] = 0x00 (bits = 0x3f, R/W bits = 0x3f)
5) buslatch[5] = 0x00 (bits = 0xff)
6) buslatch[6] = 0x00 (bits = 0xff)
7) buslatch[7] = 0x00 (bits = 0x3f, R/W bits = 0x3f)

TL>>>

Conclusion: With active SACK logic, you can successfully test the latches individually in the order 0,1,2,3,4,5,6,7.  
However, if you try to test the sequence 1,0,1, the test fails on the second attempt at latch 1.  
This only happens with latch 1 and only when you test latch 0 after latch 1 and then go back to latch 1.  
If you immediately run a SACK test again after the error, latch 1 works fine again.  

This error is reproducible on both of our Unibone boards, so a hardware fault seems unlikely to us.  

Furthermore, we then disabled the SACK logic on our Terminator by removing the right chip (N8881N) — our Terminator has socketed chips.  
After that, the result is the same as with an M930 Terminator without SACK logic:

TL>>>gst

Test SACK turnaround of M9302 terminator.
GRANT lines BG4,BG5,BG6,BG7,NPG are stimulated randomly,
if at least one is active, SACK must be asserted by M9302 terminator.
Starting now, stop with ^C ...
ERROR: GRANT line BG4_OUT active, but SACK negated!
Check:
- "SACK turn around" enabled on terminator?
Test aborted after 1 operations.

0) buslatch[0] = 0x00 (bits = 0x1f, R/W bits = 0x1f)
1) buslatch[1] = 0x00 (bits = 0x7f, R/W bits = 0x7f)
2) buslatch[2] = 0x00 (bits = 0xff)
3) buslatch[3] = 0x00 (bits = 0xff)
4) buslatch[4] = 0x00 (bits = 0x3f, R/W bits = 0x3f)
5) buslatch[5] = 0x00 (bits = 0xff)
6) buslatch[6] = 0x00 (bits = 0xff)
7) buslatch[7] = 0x00 (bits = 0x3f, R/W bits = 0x3f)

TL>>>1 o

Highspeed "moving ones" in register latch 1, stop with ^C.
^C
528666 tests successful.
0) buslatch[0] = 0x00 (bits = 0x1f, R/W bits = 0x1f)
1) buslatch[1] = 0x10 (bits = 0x7f, R/W bits = 0x7f)
2) buslatch[2] = 0x00 (bits = 0xff)
3) buslatch[3] = 0x00 (bits = 0xff)
4) buslatch[4] = 0x00 (bits = 0x3f, R/W bits = 0x3f)
5) buslatch[5] = 0x00 (bits = 0xff)
6) buslatch[6] = 0x00 (bits = 0xff)
7) buslatch[7] = 0x00 (bits = 0x3f, R/W bits = 0x3f)

TL>>>0 o

Highspeed "moving ones" in register latch 0, stop with ^C.
^C
343031 tests successful.
0) buslatch[0] = 0x1e (bits = 0x1f, R/W bits = 0x1f)
1) buslatch[1] = 0x10 (bits = 0x7f, R/W bits = 0x7f)
2) buslatch[2] = 0x00 (bits = 0xff)
3) buslatch[3] = 0x00 (bits = 0xff)
4) buslatch[4] = 0x00 (bits = 0x3f, R/W bits = 0x3f)
5) buslatch[5] = 0x00 (bits = 0xff)
6) buslatch[6] = 0x00 (bits = 0xff)
7) buslatch[7] = 0x00 (bits = 0x3f, R/W bits = 0x3f)

TL>>>1 o

Highspeed "moving ones" in register latch 1, stop with ^C.
^C
2666372 tests successful.
0) buslatch[0] = 0x1e (bits = 0x1f, R/W bits = 0x1f)
1) buslatch[1] = 0x02 (bits = 0x7f, R/W bits = 0x7f)
2) buslatch[2] = 0x00 (bits = 0xff)
3) buslatch[3] = 0x00 (bits = 0xff)
4) buslatch[4] = 0x00 (bits = 0x3f, R/W bits = 0x3f)
5) buslatch[5] = 0x00 (bits = 0xff)
6) buslatch[6] = 0x00 (bits = 0xff)
7) buslatch[7] = 0x00 (bits = 0x3f, R/W bits = 0x3f)

TL>>>* r

Highspeed random values in register latches, stops on error or by ^C.
^C
6533000 tests successful.
0) buslatch[0] = 0x06 (bits = 0x1f, R/W bits = 0x1f)
1) buslatch[1] = 0x14 (bits = 0x7f, R/W bits = 0x7f)
2) buslatch[2] = 0xba (bits = 0xff)
3) buslatch[3] = 0xeb (bits = 0xff)
4) buslatch[4] = 0x1b (bits = 0x3f, R/W bits = 0x3f)
5) buslatch[5] = 0x9a (bits = 0xff)
6) buslatch[6] = 0x8c (bits = 0xff)
7) buslatch[7] = 0x01 (bits = 0x3f, R/W bits = 0x3f)

TL>>>

Of course, without SACK logic, the SACK turnaround test doesn’t work either, but the error at latch 1 has disappeared.  
However, we’re now wondering whether this is normal, and if so, why exactly latch 1 produces an error with active SACK logic—and only when testing the 1,0,1 sequence?