New QBone Dual - Clock / KW11 Question

[Jay Jaeger]

So, I just received a couple of the brand-spanking-new QBone dual cards -- have not yet powered them up.  But I do have a couple of questions for Jean (DECRomancer):

My 11/23 CPU in a BA23 Q22 H9278A (MicroPDP11) backplane [visually verified the silk screen] has the switch for the clock.  However, I don't have any card (e.g., no BDV11) in the machine with a KW11 clock control register, just BEVNT support.  That works OK for RT11, but V7m is terribly unhappy: 

If I set it to provide a clock, then the V7m boot hangs or panics in various ways, presumably because it gets an interrupt before it is ready for it (no clock control register).  If I disable the clock, then it complains there is no clock - it loads the kernel, but notices there is no clock control register.

1)  I am looking for advice on how to set up SW2-3 and SW2-4 and/or modify the backplane and/or switch and/or software to get a working clock that V7m will accept - basically, presumably how to make the BEVNT line open (instead of driven or grounded) so that the QBone can provide a usable clock with SW2-4 ON.

2)  Can I get a schematic for the QBone Dual?

3)  Is there really a need to run the acceptance tests on a pre-built unit?  (This would mean emptying a backplane to run the tests.).  If so, I presume S3-1 and S3-2 would be on for the tests?  [Heck, if it failed, there wouldn't be much I could do except swap the transceiver boards]

Thanks.

JRJ

[Joan Touzet]

Hi Jay, thanks for the kind words (though my name's Joan, not Jean). Answers follow inline:

On Wednesday, February 5, 2025 at 5:55:25 p.m. UTC-5 Jay wrote:

My 11/23 CPU in a BA23 Q22 H9278A (MicroPDP11) backplane [visually verified the silk screen] has the switch for the clock.  However, I don't have any card (e.g., no BDV11) in the machine with a KW11 clock control register, just BEVNT support.  That works OK for RT11, but V7m is terribly unhappy: 

If I set it to provide a clock, then the V7m boot hangs or panics in various ways, presumably because it gets an interrupt before it is ready for it (no clock control register).  If I disable the clock, then it complains there is no clock - it loads the kernel, but notices there is no clock control register.

1)  I am looking for advice on how to set up SW2-3 and SW2-4 and/or modify the backplane and/or switch and/or software to get a working clock that V7m will accept - basically, presumably how to make the BEVNT line open (instead of driven or grounded) so that the QBone can provide a usable clock with SW2-4 ON.

As you already have an LTC, you should have SW2-3 and SW2-4 off. This completely isolates the backplane BEVNT line from the QBone Dual.

For reference:

* SW2-3 connects the backplane BEVNT to the QBone-driven BEVNT line, through a driver. (Currently, the QBone software has no function that actually sets a BEVNT value that I can see.) 

* SW2-4 connects the backplane BEVNT to the QBone-driven LTC, through a driver. This defaults to a 60Hz clock.

 

2)  Can I get a schematic for the QBone Dual?

We're working on making the necessary sections of this available later in the month. Having to try and get orders out pre-tariffs forced our hands to release the product a few weeks earlier than anticipated, so not everything is ready - not even the official product announcement! ;-)

3)  Is there really a need to run the acceptance tests on a pre-built unit?  (This would mean emptying a backplane to run the tests.).  If so, I presume S3-1 and S3-2 would be on for the tests?  [Heck, if it failed, there wouldn't be much I could do except swap the transceiver boards]

We run the acceptance tests for you, there is no need to run them - this is why no mention is made of them in the pack-in letter. But yes, if you want to, turn on SW3-1 and SW3-2.

Due to the extremely limited supply of ICs, we will only be providing an exchange program for failed transceiver boards, and are not selling them individually. Contact us by email directly if you need this service.

Thanks.

JRJ

[Jay Jaeger]

"As you already have an LTC, you should have SW2-3 and SW2-4 off. This completely isolates the backplane BEVNT line from the QBone Dual.

For reference:

* SW2-3 connects the backplane BEVNT to the QBone-driven BEVNT line, through a driver. (Currently, the QBone software has no function that actually sets a BEVNT value that I can see.) 

* SW2-4 connects the backplane BEVNT to the QBone-driven LTC, through a driver. This defaults to a 60Hz clock."

Thanks for the prompt reply.  Sorry about getting the name wrong.  (BIG BLUSH).

The problem is I do not have a USABLE LTC for V7m.  I just have BEVNT which is not enough for  UNIX and possibly some other operating systems that expect to have a working clock control register, and my 11/23 does not have the BDV11 ROM board DEC had which provided a way to clamp BEVNT low via a write only logic bit 6 to (and hence stop the interrupts) when that  LTC register is cleared.  

The BDV11 was available, apparently, on early Micro PDP-11's like mine (BA23 cabinet), but in my machine it is not there.  Instead, my machine has an MXV11 ROM board, and just the switch to control whether the BEVNT line comes from the power supply or is grounded.

(Ref: 1980  microcomputer interfaces handbook, BDV11)

So, I have "half" of a LTC, and V7m does not like that at all, as it cannot control the interrupt - it interrupts all the time if I have the little switch at the front panel set to provide an LTC, or has no clock at all if I have the little switch to ground BEVNT.

Without a schematic I can't be sure, but I expect that the QBone would not be well suited to clamping that signal coming from the power supply low, and I have not yet looked to see if the LTC that the QBone provides via SW2-4 is software controllable.  I'd presumably have to find a way to disconnect the BEVNT drive from the power supply to have it float so that I could turn SW2-4 on (assuming that the QBone then provides a KW11 type register.)

Software on the QBone I can presumably deal with.

JRJ

[Joan Touzet]

HI Jay,

On Thursday, February 6, 2025 at 8:56:01 a.m. UTC-5 Jay  wrote:

The problem is I do not have a USABLE LTC for V7m.  I just have BEVNT which is not enough for  UNIX and possibly some other operating systems that expect to have a working clock control register, and my 11/23 does not have the BDV11 ROM board DEC had which provided a way to clamp BEVNT low via a write only logic bit 6 to (and hence stop the interrupts) when that  LTC register is cleared.  

Hum, the v7 FAQ on minnie disagrees @ https://minnie.tuhs.org/PUPS/pupsfaq.html :

As distributed, virgin V7 expects an 11/45-style machine: 18-bit addressing with kernel, supervisor, user modes, EIS, split I/D, and around 128Kw of memory. You will need a line-frequency clock or a real-time clock (KW11-L). There is support for 11/40-style machines without supervisor mode in sys/conf. According to /usr/sys/40/README, V7 can be compiled to run ``on the 11/40, 11/60, and 11/23. It has, in fact, worked on the latter machine ... Support is included for FP11-style floating point but I can't vouch for it.''

OK, so, recompilation required. Henry says:

 

It was difficult to run V7 on a non-split-I/D machine. Possible, yes, but it required a severely cut-down kernel and was really only practical as a single-user machine. The bigger utilities (f77 is the example that comes to mind) simply could not run that way.

Note that there was a bug in V7's long-divide library routines which was largely invisible on pre-44 machines but made itself quite visible on the 44 and later CPUs.

I don't know if this was fixed in v7m, but running old UNIXes certainly exposes you to lots and lots of bugs! :-)

 

Anyway, this implies you can get what you want with a simple PDP-11/23 without the LTC register, but I have no experience with this. Maybe someone else here knows?

So, I have "half" of a LTC, and V7m does not like that at all, as it cannot control the interrupt - it interrupts all the time if I have the little switch at the front panel set to provide an LTC, or has no clock at all if I have the little switch to ground BEVNT.

For reference: the QBone Dual DIP switches do not ground BEVNT. They leave it floating on the bus. It is identical to Joerg's QBone, except that the jumper block has been replaced with a DIP switch for convenience.

 

Without a schematic I can't be sure, but I expect that the QBone would not be well suited to clamping that signal coming from the power supply low, and I have not yet looked to see if the LTC that the QBone provides via SW2-4 is software controllable.  I'd presumably have to find a way to disconnect the BEVNT drive from the power supply to have it float so that I could turn SW2-4 on (assuming that the QBone then provides a KW11 type register.)

Software on the QBone I can presumably deal with.

Just like Joerg's QBone, the QBone Dual LTC is not software controllable. You either jumper or DIP-switch it (via SW2-4) to connect it to the backplane, and then it's always driving the backplane or completely disconnected.

We intended to keep the QBone Dual 100% hardware compatible with the QBone, which is why it was implemented this way, rather than adding software LTC control and having to fork the code. (There are also very few register bits remaining for this type of control.)

If you want to try writing new software that emulates the LTC register and its enable/disable function, you'll want to set SW2-3 on (allowing BEVNT to be driven by the Linux-running software) and leave SW2-4 off. You'll then have to generate the 60Hz LTC in software as well.

-Joan @ DECromancer

 

[Jay Jaeger]

"Hum, the v7 FAQ on minnie disagrees @ https://minnie.tuhs.org/PUPS/pupsfaq.html :"

" Anyway, this implies you can get what you want with a simple PDP-11/23 without the LTC register, but I have no experience with this. Maybe someone else here knows?"

This is V7m, NOT V7.  I have loaded it using its installation process onto an RD5x (from floppy!).  It runs on Simh as an 11/23 (I used PDP11GUI to transfer my disk image to my PC to test that.).  DEC specifically supported it on an 11/23.  I have the full distribution (on floppy no less) and documentation that came from DEC back in the day that a friend provided me.    I ** ALREADY KNOW ** from both the documentation and direct experience that a working LTC clock with register control is required because 1) it fails on my hardware with no clock with a specific message  2) it fails the same way on Simh with no clock  3) it works on simh with a clock set to be a KW11L in its settings 4) it fails with a kernel panic on my hardware with a 60Hz BEVNT but no clock control (because it gets an interrupt without having the handler initialized yet).  So this is not a question at all.  (And so, I already know that just providing BEVNT with no disable in the LTC control register doesn't work.)

I have the full V7m documentation set up on my Google drive (Bitsavers hasn't copied it yet) at 

https://drive.google.com/open?id=1uFrlY5d9rW_Um1IdutIY_6Lr2desu7x6&usp=drive_fs

See the Software Technical Description Manual, page 2-3 and 2-4 for the details on how the clock has to work.  Trouble is, I have no BDV11 -- I need to emulate that by controlling BEVNT somehow,  OR a KW11L emulation - the LTC control register is the same address as a KW11L (and of course to do the latter, disable BEVNT from causing an interrupt on the processor card.)

The floppy images I provided to Bitsavers are available at https://bitsavers.org/bits/DEC/pdp11/floppyimages/rx50/ .

"I don't know if this was fixed in v7m, but running old UNIXes certainly exposes you to lots and lots of bugs! :-)"

Of course.  But old stuff is my "specialite".  https://www.computercollection.net/  That said, I'd rather not fix the kernel to put in a dummy interrupt handler during boot/initialization.  ;)  I'd rather run the software just as it was delivered.

"For reference: the QBone Dual DIP switches do not ground BEVNT. They leave it floating on the bus. It is identical to Joerg's QBone, except that the jumper block has been replaced with a DIP switch for convenience."

That much I guessed had to be that way.  My question relates to what happens if I CLOSE the switch/jumper [presumably SW2-3] for output of BEVNT at the same time the power supply is trying to drive it at 60 Hz, AND if I can also float it under software control.  From what you are saying (and without a schematic to confirm) I am guessing that this would NOT work - that either the QBone BEVNT pin driver would be unhappy pulling it to ground to override the power supply, and/or could not float it otherwise -- as a guess probably BOTH would be issues.

"If you want to try writing new software that emulates the LTC register and its enable/disable function, you'll want to set SW2-3 on (allowing BEVNT to be driven by the Linux-running software) and leave SW2-4 off. You'll then have to generate the 60Hz LTC in software as well."

Software I can deal with - there are lots of examples of devices in the Q/Unibone source.  Probably just a couple of hours effort.

The question I still have is this:  I was wondering if a QBone that had software to ground BEVNT would get upset if the power supply was trying to drive BEVNT to VCC (at 60Hz) at the same time, AND also be able float it when the interrupt enable bit is set.  This is basically what the BDV11 does: it forces BEVNT to ground if the LTC control register has interrupts disabled, and otherwise allows it to cycle.  (When I say interrupts enabled/disabled, I am referring to bit 6 of a LTC interrupt control register (KW11L / BDV11).

If the driver on the QBone BEVNT line would not get upset pulling BEVNT to ground under software control to override the power supply trying to drive it high at 60Hz AND would be also able to float it under software control, then all I need is software to respond to the right address, and then either drive BEVNT to ground when interrupts are disabled or float it if interrupts are enabled, allowing the power supply signal to do its thing.  If the drivers could not handle that, then I'd also need to 1) change my hardware to disconnect BEVNT from the power supply floating AND 2) write software to provide the LTC control register and the 60Hz BEVNT and the interrupt.

Hmmm:  A little research for me:  If I configure the processor card to ignore BEVNT (I think there might be a jumper for that), and tell the QBone to accept BEVNT as an *INPUT*, and then write software to provide the interrupt and the associated enable/disable control, that might work - and I wouldn't have to worry about trying to generate the 60Hz signal in software -- IF the QBone's drivers will let me see BEVNT as an input without trying to drive it.  Otherwise I'd have to clamp BEVNT / tell the processor to ignore it and provide all of the 60Hz input, interrupt and control in software (i.e., a full KW11L emulation.)

Thanks for the info Joan -- I probably have all that I need to know at this point, unless the QBone can Ground BEVNT *and* float BEVNT under software control.

JRJ

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[Jay Jaeger]

OK, so I did some more research.

YES, I can tell (remove a jumper) to tell the PDP-11/23 processor CPU card to NOT generate an LTC interrupt from BEVNT - it would just ignore BEVNT.

So, the last question before I start thinking about KW11/BDV11 LTC register and interrupt emulation software on the QBone:  Is there a way / what switches should I set so that the 60Hz power supply signal on BEVNT can be used by the QBone as an INPUT (I don't want it to be an output if the power supply is providing the 60Hz on BEVNT, of course).  Does SW2-3 connect BEVNT to a bidirectional driver to the BBB that I could simply never drive and just use that BEVENT pin as an INPUT?

That way would be best, as I would not have to generate the actual 60Hz signal in the QBone itself and the PDP-11/23 dip switch for controlling BEVNT would still work as designed - I'd just have to implement a simple control register (interrupt enable/disable) and if enabled, interrupt on the rising edge of each BEVNT clock (perhaps with some debouncing).

Or is there no way to do that, and I would then also have to generate the 60Hz inside the BBB (and have the 11/23 front panel dip switch just ground BEVENT), and have SW2-3 and SW-4 both off?

Thanks.

JRJ

[Mark Matlock]

Jay,

    The QBone/UniBone already has a software KW11 emulator. In most of the OS examples it is disabled, but if you do a ld command after a script finishes you should see a kw11 device that can be enabled.

     It is mentioned at Joerg’s website in a list of devices:

https://retrocmp.com/projects/qbone/313-qbone-introduction

Best,

Mark

On Feb 16, 2025, at 9:14 PM, Jay Jaeger <cub...@gmail.com> wrote:



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[Jay Jaeger]

Thanks for the reminder.  I must have known that at one time, I think, because I wired up a 555 60Hz clock signal on my first Unibone and tested the clock on my bare DD11 backplane.  But I didn't see it offhand when I went looking recently.

A quick look at the link you provided indicates it is a DL11-W - and I won't want the DL11 part of that as it would conflict with my real hardware, so I may need to copy and tweak it if it doesn't already have provision for being just the KW11 register or for putting the SLU and its interrupt vector to alternative addresses.  And it presumably still needs a 60Hz (or 60Hz where appropriate) input signal - so my question for Joan (decromancer QBone) remains.

JRJ

[Joan Touzet]

Closing SW2-3 and opening SW2-4 is identical to the classic QBone design with the 50Hz jumper off.

[Jay Jaeger]

OK.  With an ohmmeter I see that having SW2-3 OFF disconnects the bus driver from BEVNT.  That is definitely a "good thing" as having SW2-3 OFF keeps it from having a bus conflict between the BEVNT from the power supply (or ground, if the switch behind the front panel is set that way) and the bus driver in the QBone whenever BUS_ENABLE_L is enabled.  So, I absolutely need to leave SW2-3 OFF or I'd risk damage to the bus driver on the QBone.

What I would want, in an ideal world, would be a way to connect BEVNT to an I/O pin through a bus *receiver* - that never tried to drive BEVNT.  Then I could pull the jumper on my processor card, enable BEVNT on my front panel  and use it as input to the KW11-L (part of the DW11-L simulation module) inside the QBone,  but the present design doesn't seem to allow for that.

But the way it is is definitely OK, and now I know how to get what I want.  The KW11-L simulation code in the QBone can use an internally generated timer, and I can set my switch behind the front panel to ground BENVT so that the processor card doesn't try to generate an interrupt (without having to remove the jumper on the processor card.)

JRJ

[Jay Jaeger]

SUCCESS.  All I had to do was turn ON the BEVNT LTC switch at the front panel,  run demo.sh and enable the kw11, and V7m came to life, then set the terminal settings to 9600bps.

Fri Mar 29 22:37:36 EST 1991

ERROR LOG has - 40 of 40 blocks used

login: root

Welcome to V7M-11 V1.0

erase = delete, kill = ^U, intr = ^C
# stty
speed 9600 baud
erase = ^?; kill = ^U; intr = ^C; quit = ^\
start = ^Q; stop = ^S; eof = ^D; brk = M-^?
even odd -raw -nl echo -lcase -tabs -cbreak -tandem
-crtbs crterase crtkill ctlecho -prterase

(Note: at least so far, it panics if I just have the real memory (realmem=253952) when I try to go to multi-user mode, but works OK if I do the usual >>>m i to provide full memory

which results in realmem=3932160).  I have yet to thoroughly test the physical memory in the box, though).

JRJ