Cheap Logic Analyser

[Fred Jan Kraan]

Since some time I am constructing and experimenting with a simple multi-channel logic analyser based on the Gusmanb design. This allows up to 120 channels based on some Raspberry Pi Pico boards and level converters. So far I only tested it with simple 8-bit computers, but it might also be usable for PDP-11 debugging.

Because the complete analyser is so small, it could be very close to the backplane and boards and need relatively short wires. The software is multi-platform and works very well on Linux. The trigger facilities are a bit simple. With the standard Pico 100MHz is possible, with a Pico 2 400 MHz is advertised.

Could there be a reason it might not work for a Qbus PDP-11?

Greetings,

Fred Jan

[Joerg Hoppe]

Fred,

> Since some time I am constructing and experimenting with a simple
> multi-channel logic analyser based on the Gusmanb design. This allows
> up to 120 channels based on some Raspberry Pi Pico boards and level
> converters. So far I only tested it with simple 8-bit computers, but
> it might also be usable for PDP-11 debugging.

Great, great news!
Is there a web page?

>
> Because the complete analyser is so small, it could be very close to
> the backplane and boards and need relatively short wires. The software
> is multi-platform and works very well on Linux. The trigger facilities
> are a bit simple. With the standard Pico 100MHz is possible, with a
> Pico 2 400 MHz is advertised.
>
> Could there be a reason it might not work for a Qbus PDP-11?

Signal levels? PDP-11 is a 5V TTL world ... the RPis are 3.3V

Here a wish list, most is critical for PDP-11 debugging:
- channel count. UNIBUS needs 56 wires alone, add 20+ more for a complex
debugging task
Channel count is always a big problem for existing logic analyzers
(below the $5000 mark).
- probe wires must be pluggable to these 3M DIL clips, or other fasteners
- bundling of multiple wires to logical signals (BDAL22:0, DATA15:0)
- trigger logic can't be complex enough ... to catch UNIBUS/QBUS cycles
you need a mix of level conditions as well as edge triggers
- record data before and after a trigger
- long trace memory ... not a problem for a RPi
- speed: 100MHz is enough, for TTL switching speed. But faster would be
better.
- ease of operation: you *really* are at the edge of your skills when
going into defective PDP-11 logic.
    So do not fight with the analyzer too.

thanks again, kind regards,

Joerg

[Three Jeeps]

Having spent a fair amount of time with PDP11s connected to logic analyzers I can offer some points for your consideration.

To (relatively) quickly diagnose a problem the LA has to support many triggering combinations/specifications.  I visited Dr Gusmans website and did a quick look at the software.  It seems very basic.  Not clear how useful this will be. I suspect for finding missing signals it should be fine e.g. a stuck at conditions.   You will probably need a combination of level and edge triggering conditions on sets or subsets of the channels. At first blush, the triggering combinations seem rather basic.

The LA is very rudimentary from a hw perspective. There may be times when you will want to look at a large number of signals, e.g. all the address and data lines, interrupt lines, bevent, etc. You will need a lot of channels - approximately 50-60 lines. A extender card will be very useful for component level debugging at the on-board level.

Wire test lead management and integrity may be an issue (50-60+ probe wires) - you may need to make special adapters to grab signals with on board connectors.  To keep the proper signal integrity and timing, the probe wires should not be extended.

IMHO, the probe connection method is probably OK for 8-16 channels on a breadboard but will cause you headaches looking at large number of signals.

From what I've read, the channel level shifting buffers can interface to 5 (5.5 VDC).  PDP11s use 5 vdc TTL levels so the LA should be able to work with the PDPs.

It seems the sampling rate is more than sufficient to work.  Expandability of signal lines is sufficient, Memory depth may be an issue because  you may need to have a deep set of data after the event.

On  Gusmanb github repo he describes an interesting hw problem on the Pico2 with GPIO lines- GPIO hardware that locks the pins whenever you input a high level, what is known as "Errata E9". According to the official errata the lock only happens when the pull downs are enabled, you input a high level value and then the GPIO starts outputting 2.1v. He supposedly got around this issue and qualifies the fix as still being tested.  This puts some doubt in my head about the believably of the data being displayed by the LA.....

If you go ahead and try using the LA on a PDP11, I'd be interested in hearing about your experience.

J

[Ashlin Inwood]

If you'd like any help, I would be keen to assist with any project. The existing project is good, but it's an extremely inconvenient form factor for us who want a larger number of channels. It's also not particularly mechanically compatible with the Uniprobe/QProbe.

There is a nice case and USB hub for this, but that is just a workaround for the inconvenient form factor:
https://github.com/gusmanb/logicanalyzer/discussions/157

[Fred Jan Kraan]

Hi,

Thanks for the responses. At one time I will try to make a setup to connect to the QBus. The JasonYANG variant of the board isn't that bad of a form factor, as it is just 7mm high and about 5 by 5 cm. The plan is to attach then to a custom short QProbe-like board with just the connectors, no CLPDs. It might even fit inside the card-cage. I'll research some more before start making boards. With three boards there should be enough channels (72).

Greetings,

Fred Jan

[Joerg Hoppe]

Am 28.03.2025 um 13:32 schrieb Fred Jan Kraan:

Hi,

Thanks for the responses. At one time I will try to make a setup to connect to the QBus. The JasonYANG variant of the board isn't that bad of a form factor, as it is just 7mm high and about 5 by 5 cm. The plan is to attach then to a custom short QProbe-like board with just the connectors, no CLPDs. It might even fit inside the card-cage. I'll research some more before start making boards. With three boards there should be enough channels (72).

Checkout my https://retrocmp.com/tools/qprobe
and
https://retrocmp.com/tools/qprobe/327-qprobe2023-overview

kind regards,

Joerg

Greetings,

Fred Jan

On Wednesday, March 26, 2025 at 8:37:32 AM UTC+1 ashlin...@gmail.com wrote:

If you'd like any help, I would be keen to assist with any project. The existing project is good, but it's an extremely inconvenient form factor for us who want a larger number of channels. It's also not particularly mechanically compatible with the Uniprobe/QProbe.

There is a nice case and USB hub for this, but that is just a workaround for the inconvenient form factor:
https://github.com/gusmanb/logicanalyzer/discussions/157

On Wednesday, March 26, 2025 at 3:36:17 AM UTC+13 jjhu...@gmail.com wrote:

Having spent a fair amount of time with PDP11s connected to logic analyzers I can offer some points for your consideration.

To (relatively) quickly diagnose a problem the LA has to support many triggering combinations/specifications.  I visited Dr Gusmans website and did a quick look at the software.  It seems very basic.  Not clear how useful this will be. I suspect for finding missing signals it should be fine e.g. a stuck at conditions.   You will probably need a combination of level and edge triggering conditions on sets or subsets of the channels. At first blush, the triggering combinations seem rather basic.

The LA is very rudimentary from a hw perspective. There may be times when you will want to look at a large number of signals, e.g. all the address and data lines, interrupt lines, bevent, etc. You will need a lot of channels - approximately 50-60 lines. A extender card will be very useful for component level debugging at the on-board level.

Wire test lead management and integrity may be an issue (50-60+ probe wires) - you may need to make special adapters to grab signals with on board connectors.  To keep the proper signal integrity and timing, the probe wires should not be extended.

IMHO, the probe connection method is probably OK for 8-16 channels on a breadboard but will cause you headaches looking at large number of signals.

From what I've read, the channel level shifting buffers can interface to 5 (5.5 VDC).  PDP11s use 5 vdc TTL levels so the LA should be able to work with the PDPs.

It seems the sampling rate is more than sufficient to work.  Expandability of signal lines is sufficient, Memory depth may be an issue because  you may need to have a deep set of data after the event.

On  Gusmanb github repo he describes an interesting hw problem on the Pico2 with GPIO lines- GPIO hardware that locks the pins whenever you input a high level, what is known as "Errata E9". According to the official errata the lock only happens when the pull downs are enabled, you input a high level value and then the GPIO starts outputting 2.1v. He supposedly got around this issue and qualifies the fix as still being tested.  This puts some doubt in my head about the believably of the data being displayed by the LA.....

If you go ahead and try using the LA on a PDP11, I'd be interested in hearing about your experience.

J

On Tuesday, March 25, 2025 at 8:26:17 AM UTC-4 fjk...@electrickery.nl wrote:

Since some time I am constructing and experimenting with a simple multi-channel logic analyser based on the Gusmanb design. This allows up to 120 channels based on some Raspberry Pi Pico boards and level converters. So far I only tested it with simple 8-bit computers, but it might also be usable for PDP-11 debugging.

Because the complete analyser is so small, it could be very close to the backplane and boards and need relatively short wires. The software is multi-platform and works very well on Linux. The trigger facilities are a bit simple. With the standard Pico 100MHz is possible, with a Pico 2 400 MHz is advertised.

Could there be a reason it might not work for a Qbus PDP-11?

Greetings,

Fred Jan

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