On Mon, 12 Dec 2022, Joerg Hoppe wrote:
> Hi Steven and all,
>
> lookslike something bad in the DMA timing ... anybody else suffering from
> this?
>
> Special to Steven is the modified Heath H-11 system.
>
> For debugging it would be nice to see this on a DEC system.
>
> Steven, you say this is "becoming chronic".
> This may be an indicator of something going to fail in the M8192,
> or other parts of your system. Can you swap the M8192 ... or the QBone?
> It maybe even a power supply issue or a backplane contact.
That's possible, but I've had these on and off since the beginning and did
see them with the original LSI-11/03 CPU. I think the reason they are
more prevelant now is that I'm running very disk intensive environments.
I will check the power supply, but have no means of swapping the QBone.
> For the logic analyzer, you would generate a GPIO trigger signal before the
> assertion:
> // set pin associated with LED 1 to catch "good" DMA cycles
> ARM_DEBUG_PIN2(1) ;
> if (dmareq != NULL)
> ARM_DEBUG_PIN3(1) ; // set pin associated with LED 3 for error
> assert(dmareq != NULL);
> ARM_DEBUG_PIN2(0) ;
So, this new bit of code needs to be added the qunibusadapter.cpp at or
around line 1011?
> The trace should show at least the QBUS IRQ and DMA signals.
> One would make multiple shots and compare the regular good DMA cycles with
> the deadly one.
I'll setup to grab a trace.
If anyone else has thoughts, let me know?
Steve
> @Steven: can you add your backplane
The backplane is a Heath product that's roughly equivalent to an H9270,
but completely based on a double-sided PCB - no wirewrap pins. I brought
through BA18-BA21 using #30 wirewrap wire (following the serpentine path).
I found that Heath presented the LTC signal only on the 4 right-hand
positions and added a jumper to ensure that all slots receive the signal.
Could that possibly be a problem? But, again, I was seeing the assert
fail with an unmodified backplane and M7264 CPU.
The only other mod was to wire-OR AF1 and AH1 to accommodate variation in
where the CPUs present SRUN.
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