Applied Bias

[Artur]

In the lecture, prof. said that our design will be tested for different
applied bias.
and in one of the post in the newsgroup, prof. also said that we can't
assume const. bias in the structure,
so, does it mean that we have to test our design for different bias such
that the device operates in sat, linear mode?
and what is the max. applied bias that our design will be tested for?
thanks.

[Vivek Subramanian]

Your design will need to work in all regions, including saturation and
linear; otherwise, you won't be able to generate the requisite plots.

All specs will be evaluation at edge-of-saturation @ IC = 1mA. Since there
is a spec. for early voltage, breakdown, etc., these will determine the
limits over which your design will need to work.

Note the explanation in the project handout re: how to deal with excess
forward bias conditions (i.e., make sure the bias never exceeds Vbi for any
junction).

-VS.

"Artur" <art...@berkeley.edu> wrote in message
news:gh6t7m$2of4$1...@geode.berkeley.edu...

[Artur]

but then where is the applied bias being applied to?
we have 2 pn junctions, BE and BC
but Vbe is not equal to Vbc,
so how can we do that if VA is const.?
the device only work in sat. edge because Vbc=0 ?
how do we bias the device to work in linear?
thanks

"Vivek Subramanian" <viv...@eecs.berkeley.edu> wrote in message
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