when do instructions get fetched in pipeline?

[Stephen Tu]

my question draws its inspiration from the fall 2005 final. this
pertains to part A of question F3. How do we determine when the next
instruction initially gets fetched in the pipeline. i ask this question
because of what appears to be a discrepancy in the answer key. that is,
instruction 3 gets fetched in clock cycle 3, which marks the first of a
series of decoding stages for instruction 2. however, instructions 4 and
5 do not get fetched until cycles 8 and 11 respectively, which marks the
last of a series of decoding stages for their previous instructions
respectively.

i hope that wasn't worded too poorly. basically i'm asking why the F for
instruction 3 comes under the first D for instruction 2, but the F's for
instructions 4 and 5 don't come until the last D of their respective
previous instructions

thanks!

[[TA] Omar Akkawi]

OK, so for those types of diagrams, it isn't *too* important where you
draw the fetch happening. More important is the number of stall needed
for each instruction.

To accurately indicate *when* the actual fetch happens, you would need
to know *how* the processor implements it's stalls. So, don't be overly
concerned with the exact location. For any such diagram that you may or
may not have to fill in for the final, be more concerned with indicating
where the Fetch would happen if there weren't any stalls, and showing
the number of stalls that occur.

- Omar Akkawi, CS 61C TA, Summer 2008