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narang....@gmail.com
Oct 29, 2012, 7:51:45 AM10/29/12
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hey friends..can you please help me by posting Verilog code and test bench of this question.
https://inst.eecs.berkeley.edu/~cs150/fa07/Protected/HW5-soln.pdf
The question 6 in this pdf is the same question and is given with the FSM model. But I need verilog code and test bench also.
Please Help!
Thanks!!
Draw the State Transition Diagrams for the controllers below. Controller 1 is the data producer; it streams a sequence of values to the shared, single word buffer. Concretely, it reads the value from the memory location pointed to by the memory pointer, places it in the next value register, and sets the valid bit to inform the consumer that the shared buffer is full. It increments the memory pointer before reading the next word. Controller 2 is the data consumer; it takes the value from the next value register when valid, clears the valid bit, accumulates the value and places it in the accumulated value register. The true controllers operate independently and run and potentially different rates. The producer cannot over-write the buffer until it has been emptied, and the consumer cannot read it until it is full. Be careful to design the FSM’s such that memory locations are not added in multiple times in a row and that values are not lost.
Note that this problem is a little bit open ended. You will need to specify the inputs and outputs of your two cooperating state machines, as well as determining the symbolic states and the functional behavior.
https://inst.eecs.berkeley.edu/~cs150/fa07/Protected/HW5-soln.pdf
The question 6 in this pdf is the same question and is given with the FSM model. But I need verilog code and test bench also.
Please Help!
Thanks!!
Draw the State Transition Diagrams for the controllers below. Controller 1 is the data producer; it streams a sequence of values to the shared, single word buffer. Concretely, it reads the value from the memory location pointed to by the memory pointer, places it in the next value register, and sets the valid bit to inform the consumer that the shared buffer is full. It increments the memory pointer before reading the next word. Controller 2 is the data consumer; it takes the value from the next value register when valid, clears the valid bit, accumulates the value and places it in the accumulated value register. The true controllers operate independently and run and potentially different rates. The producer cannot over-write the buffer until it has been emptied, and the consumer cannot read it until it is full. Be careful to design the FSM’s such that memory locations are not added in multiple times in a row and that values are not lost.
Note that this problem is a little bit open ended. You will need to specify the inputs and outputs of your two cooperating state machines, as well as determining the symbolic states and the functional behavior.
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