Ultimate Audio Four Master

[Gaby Zenz]

Im working on a new project and I'm trying to use the PCM5122 DAC clocked by a 12 MHz oscillator as I2S master (the DAC generates BCK and LRCK signals). My goal is to achieve what stated at page 22 of PCM5122 datasheet which says:

"SCK rates that are not common to standard audio clocks, between 1MHz and 50MHz, are only supported in software mode by configuring various PLL and clock-divider registers. This programmability allows the device to become a clock master and drive the host serial port with LRCK and BCK, from a non-audio related clock (for example, using 12MHz to generate 44.1kHz (LRCK) and 2.8224MHz (BCK) )."

1) How it's possible to generate precise BCK and LRCK from a 12 MHz source if BCK and LRCK outputs are generated from SCK only?

BCK and LRCK dividers should be clocked by the PLL output not directly from SCK. In fact I'm only able to generate LRCK and BCK by dividing the 12 MHz SCK leading to unprecise results. I'm sure I'm missing something.

2) SRCREF register is meant to select the clock input for the PLL between 4 different possibilities. If you look at register 13 description (page 81 on the datasheet) you got simply the bit 4 that le you choose between SCK and BCK as PLL clock input

3) In figure 26 there is a SRCDAC to route clock to DAC, charge pump and digital filter modules. The point here is that SRCDAC register does not exists or is completely missing from the documentation. So, the question is, where the DACCK comes from?

Even with the above problems I did my best to let the PCM5122 acting as I2S master using PLL mode (trying to play at 44100 KHz 16 bit). The registers config I'm using without success are the following:

I got 12 MHz output on both LRCK and BCK (leaving their dividers as 0x00) and no CPCK. If I set the BCK and LRCK dividers to values different from 0 I got 990.312 KHz as charge pump clock.

The clock is obviously not correctly routed and the PLL is not clocking the LRCK and BCK signals but I'm not able to see what's wrong (please note that I'm using values from datasheet example to set PLL coefficients P, J and D).

Sorry for the very long post, I hope someone is able to fill the holes in the datasheet as TI support told me to report my problems on the forum!

Thanks in advance

Best Regards

Marco

thank you for going through the datasheet in such fine detail. I understand the issue you're having, and will work with one of the application engineers for the product to respond to you. The PCM512x and 4x datasheets are going through a cleanup in the next few weeks. I hope to have more details on this application very soon. (of course, we'll answer in this thread before the datasheet gets updated!)

Glad to hear you DAfydd,

thank you for your clarification. I would like to use a 12 MHz DIGITAL OSCILLATOR which should be connected to a 1 pin only, is it possible or I have to use a crystal connected between 2 GPIO pins? Let me know what is supported and what do you suggest. GPIO4 and GPIO5 in my opinion are good candidates to input the 12 MHz to the chip if 2 pins are required (GPIO3 is better if only one pin is enough using a digital oscillator).

but the datasheet reports that in order to disable the Auto clock feature I have to write a 1. Could you confirm which way is correct please?

Another thing which is not clear to me is the register to use for setting the PLL reference clock to GPIO:

is it register 18 or 0x08 or another?

In your opinion, after setting these register values should I expect immediately something out from GPIO6 or do I need at least to enable the PLL (register 4 set to 1)?

Thanks a lot for your assistance

Regards

Marco

Hi Dafydd,

Finally I got the DAC working thanks to your istructions. There are some details to improve but the system now is working. I hope to view the updated datasheet when I'll be back from my summer holidays!

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