VLSI Verification Engineer Fulltime/Perm Opening

[qhadeerm Systel]

Hi,

Hope you are doing good. We have the below open Multiple full time or permanent position open with one of our client. Please revert back to me if you are available & interested in below opportunity with word version of your resume, best time & number to contact you. Please feel free to contact me to discuss more about this opportunity.

To know more about us, please visit www.systelinc.com.

Position 1:
Position: VLSI Verification/Design Verification Engineer
Location: Raleigh, North Carolina & Austin Texas
Duration: Full Time/Permanent
Experience Level: 5-10 Years

Education: Required: Bachelors, Computer Engineering and/or Computer Science and/or Electrical Engineering
Preferred: Masters, Computer Engineering and/or Computer Science and/or Electrical Engineering or equivalent experience- 3+ year

Job Description:
Must have experience in System Verilog and either UVM (preferred) or OVM. 3+ years of experience in ASIC/SoC Verification
Strong knowledge in Object Oriented programming, data structures, and algorithms.
Strong knowledge of HVLs(VERA/e/SystemVerilog), HDLs(Verilog/VHDL), C/C++.
Must have hands-on experience and strong knowledge on HVL methodology (UVM, OVM, VMM, RVM), testbench automation, industry standard bug tracking, and regression mechanisms.
In-depth knowledge in SoC architecture, including CPUs (preferably ARM), memory subsystems and controllers (PCDDRx), peripherals (PCIe, SATA, Ethernet) , multi-domain clocking, and bus & interconnect structures (preferably as AHB and AXI).
Must have excellent system debug skills.
Excellent oral and written communication skills.
Ability to work in a team environment.

Thanks
Qhadeer
6788253299
qhad...@systelinc.com