[PATCH v4 00/23] x86: Trenchboot Secure Launch DRTM (Xen)

[Sergii Dmytruk]

The aim of the [TrenchBoot] project is to provide an implementation of
DRTM that is generic enough to cover various use cases:
- Intel TXT and AMD SKINIT on x86 CPUs
- legacy and UEFI boot
- TPM1.2 and TPM2.0 (TIS and CRB)
- (in the future) DRTM on Arm CPUs

DRTM is a version of a measured launch that starts on request rather
than at the start of a boot cycle. One of its advantages is in not
including the firmware in the chain of trust.

Xen already supports DRTM via [tboot] which targets Intel TXT only.
tboot encapsulates some of the DRTM details within itself while with
TrenchBoot Xen (or Linux) is meant to be a self-contained payload for a
TrenchBoot-enabled bootloader (think GRUB). The one exception is that
UEFI case requires calling back into bootloader to initiate DRTM, which
is necessary to give Xen a chance of querying all the information it
needs from the firmware before performing DRTM start.

From reading the above tboot might seem like a more abstracted, but the
reality is that the payload needs to have DRTM-specific knowledge
either way. In principle, TrenchBoot, allows coming up with
independent implementations of bootloaders and payloads that are
compatible with each other.

The "x86/boot: choose AP stack based on APIC ID" patch is shared with
[Parallelize AP bring-up] series and is required here because Intel TXT
always releases all APs simultaneously. The rest of the patches are
unique.

This version of the patches corresponds to this branch:
https://github.com/TrenchBoot/xen/compare/7c77acd452fb...tb-staging-2026-07-31-v4

-----

[TrenchBoot]: https://trenchboot.org/
[tboot]: https://sourceforge.net/p/tboot/wiki/Home/
[Parallelize AP bring-up]: https://lore.kernel.org/xen-devel/cover.1699982111....@3mdeb.com/
[v1]: https://lore.kernel.org/xen-devel/cover.1745172094....@3mdeb.com/
[v2]: https://lore.kernel.org/xen-devel/cover.1747155790....@3mdeb.com/
[v3]: https://lore.kernel.org/xen-devel/cover.1748611041....@3mdeb.com/

-----

Changes in v4:
- added notes to individial commits, the notes below cover some of
more generic changes or those spanning multiple commits
- dropped SHA-1 changes (was committed independently of this patchset)
- added CONFIG_SLAUNCH Kconfig option
- TPM driver changes have been moved to the front and are now
independent from TPM event log and the rest of this patchset in
general
- a few commits were split, joined and/or renamed to make changes more
independent, see notes in individual patches
- added support for communicating with TPM2.0 via CRB and memory
protection using TPR to support newer handware
- moved UEFI_SLR_TABLE_GUID from xen/include/xen/slr-table.h to
xen/common/efi/boot.c
- changed the code for dealing with tables in TXT heap to be iterative
- added more implementation-specific error codes and removed unused
ones
- extracted declarations from tpm.c into headers for TPM1.2 and TPM2.0
- return EACCES instead of EPERM when refusing to go into S3 state
- moved SLAUNCH_BOOTLOADER_MAGIC from x86/asm/intel-txt.h to
x86/boot/head.S
- moved making MTRR-related functions public to commit which uses them
- use container_of() after slr_next_entry_by_tag() instead of a cast
- made more code that deals with SLRT const-correct (including adding
const to the parameter of dl_handler_func)
- absent TPM event log is now consistently allowed by both TPM1.2 and
TPM2.0 implementations

Changes in [v3]:
- sorted `F:` entries in MAINTAINERS file
- made sha1 implementation more similar to sha256
- dropped unused parameter from
xen/arch/x86/cpu/intel.c:intel_log_smx_txt()
- updated header guards according to new style
- xen/arch/x86/include/asm/intel-txt.h:
+ briefly explained what TXT is
+ renamed: NR_TXT_CONFIG_SIZE -> TXT_CONFIG_SPACE_SIZE
+ renamed: read_txt_reg() -> txt_read()
+ renamed: write_txt_reg() -> txt_write()
+ marked txt_reset() as noreturn and used unreacheable() instead of
while(1)
+ explained a bit more about TXT Heap
- xen/include/xen/slr-table.h:
+ briefly explained what SLRT is
+ fixed checks in slr_next_entry()
- SPDX-License-Identifier: GPL-2.0 -> GPL-2.0-only
- made more code const-correct
- use arithmetic on pointers to `void` instead of pointers to
`uint8_t`

Changes in [v2]:
- using dashes instead of underscores in the names of new files
- dropping of an extra sha256 implementation
- rewriting sha1 implementation to be in line with already present
sha256 implementation (simplifying it and getting rid of macros)
- correct placement of new lines in Makefile
- add header guards to all new files
- use correct names for header guards in new files
- update license of xen/include/xen/slr-table.h
- changed fixmlehdr to search for header within 8 instead of 4 KiB
file prefix
- don't print DRTM-related capabilities when resuming from S3
- forbade S3 in case of Secure Launch
- fixed an issue with resuming from S3 caused by inappropriate use of
__initdata
- added a new section to MAINTAINERS
- improved commit messages
- fixed MISRA C violations:
+ shadowing of e820 global
+ missing U literal suffixes
+ use of ull literal suffix
+ excluded fixmlehdr from analysis (similar to other build tools)
+ use of 0 instead of NULL in one place
+ provided declarations for some definitions
+ marked asm-invoked functions with `asmlinkage`

-----

Kacper Stojek (2):
x86/boot: add CONFIG_SLAUNCH, MLE header and Secure Launch entry point
xen/arch/x86: reserve TXT memory during Slaunch

Krystian Hebel (7):
x86/tpm.c: hashing and extending PCRs for TPM1.2
x86/include/asm/intel-txt.h: constants and accessors for TXT registers
and heap
x86/boot/slaunch-early: early Intel TXT sanity checks
x86/slaunch: restore boot MTRRs after Intel TXT DRTM
x86/slaunch: measure MBI into TPM
x86/boot: choose AP stack based on APIC ID
x86/smpboot.c: TXT AP bringup

Michał Żygowski (2):
x86/cpu: report SMX, TXT and SKINIT capabilities
x86/hvm: check for VMX in SMX if Slaunch is active

Sergii Dmytruk (10):
x86/mtrr: get rid of a static variable on pause/restore
x86/tpm.c: support extending PCRs of TPM2.0 via TIS
include/xen/slr-table.h: Secure Launch Resource Table definitions
x86/boot/slaunch-early: implement early initialization
x86/slaunch: update TPM event log (TPM1.2 or TPM2.0)
x86/slaunch: process DRTM policy
x86/acpi: disallow S3 on Secure Launch boot
x86/slaunch: support AMD CPUs
x86/slaunch: support EFI boot
MAINTAINERS: add a section for TrenchBoot Slaunch

Szymon Acedański (2):
x86/tpm.c: add CRB interface support
xen/arch/x86: add TPR (TXT Protected Range) DMA protection support

.gitignore | 1 +
MAINTAINERS | 19 +
.../eclair_analysis/ECLAIR/out_of_scope.ecl | 1 +
docs/hypervisor-guide/x86/how-xen-boots.rst | 12 +
xen/arch/x86/Kconfig | 8 +
xen/arch/x86/Makefile | 16 +-
xen/arch/x86/acpi/power.c | 8 +
xen/arch/x86/boot/Makefile | 22 +-
xen/arch/x86/boot/head.S | 267 ++++++
xen/arch/x86/boot/slaunch-early.c | 104 +++
xen/arch/x86/boot/trampoline.S | 42 +-
xen/arch/x86/boot/x86_64.S | 67 +-
xen/arch/x86/cpu/amd.c | 16 +
xen/arch/x86/cpu/cpu.h | 1 +
xen/arch/x86/cpu/hygon.c | 1 +
xen/arch/x86/cpu/intel.c | 50 +
xen/arch/x86/cpu/mtrr/generic.c | 50 +-
xen/arch/x86/e820.c | 5 +
xen/arch/x86/efi/efi-boot.h | 95 +-
xen/arch/x86/efi/fixmlehdr.c | 127 +++
xen/arch/x86/hvm/vmx/vmcs.c | 3 +-
xen/arch/x86/include/asm/apicdef.h | 4 +
xen/arch/x86/include/asm/intel-txt.h | 573 ++++++++++++
xen/arch/x86/include/asm/msr-index.h | 3 +
xen/arch/x86/include/asm/mtrr.h | 8 +
xen/arch/x86/include/asm/processor.h | 1 +
xen/arch/x86/include/asm/setup.h | 3 +
xen/arch/x86/include/asm/slaunch-tpm.h | 26 +
xen/arch/x86/include/asm/slaunch.h | 128 +++
xen/arch/x86/include/asm/tpm.h | 74 ++
xen/arch/x86/include/asm/tpm1.h | 94 ++
xen/arch/x86/include/asm/tpm2.h | 150 +++
xen/arch/x86/intel-txt.c | 197 ++++
xen/arch/x86/setup.c | 32 +-
xen/arch/x86/slaunch-tpm.c | 312 +++++++
xen/arch/x86/slaunch.c | 478 ++++++++++
xen/arch/x86/smpboot.c | 75 ++
xen/arch/x86/tboot.c | 20 +-
xen/arch/x86/tpm.c | 862 ++++++++++++++++++
xen/arch/x86/x86_64/asm-offsets.c | 13 +
xen/common/efi/boot.c | 6 +
xen/common/efi/runtime.c | 1 +
xen/include/xen/efi.h | 1 +
xen/include/xen/slr-table.h | 272 ++++++
44 files changed, 4191 insertions(+), 57 deletions(-)
create mode 100644 xen/arch/x86/boot/slaunch-early.c
create mode 100644 xen/arch/x86/efi/fixmlehdr.c
create mode 100644 xen/arch/x86/include/asm/intel-txt.h
create mode 100644 xen/arch/x86/include/asm/slaunch-tpm.h
create mode 100644 xen/arch/x86/include/asm/slaunch.h
create mode 100644 xen/arch/x86/include/asm/tpm.h
create mode 100644 xen/arch/x86/include/asm/tpm1.h
create mode 100644 xen/arch/x86/include/asm/tpm2.h
create mode 100644 xen/arch/x86/intel-txt.c
create mode 100644 xen/arch/x86/slaunch-tpm.c
create mode 100644 xen/arch/x86/slaunch.c
create mode 100644 xen/arch/x86/tpm.c
create mode 100644 xen/include/xen/slr-table.h


base-commit: 7c77acd452fb6a3079661e75ebb5cf23ed985cc7
--
2.55.0

[Sergii Dmytruk]

In addition to keeping the state in one place instead of on stack and in
a static variable, this enables exposing this functionality to other
units in the future.

Signed-off-by: Sergii Dmytruk <sergii....@3mdeb.com>
---

Notes:
v4: was called "x86/mtrr: expose functions for pausing caching"
v4: no longer makes anything public, just updates implementation
v4: the state structure is now an output parameter instead of a return value
v4: switches from rdmsrl() to rdmsr() on one line that's updated anyway

xen/arch/x86/cpu/mtrr/generic.c | 55 +++++++++++++++++----------------
1 file changed, 28 insertions(+), 27 deletions(-)

diff --git a/xen/arch/x86/cpu/mtrr/generic.c b/xen/arch/x86/cpu/mtrr/generic.c
index 23c279eb9a..86eb0f405b 100644
--- a/xen/arch/x86/cpu/mtrr/generic.c
+++ b/xen/arch/x86/cpu/mtrr/generic.c
@@ -14,6 +14,11 @@
#include <asm/cpufeature.h>
#include "mtrr.h"

+struct mtrr_pausing_state {
+ bool pge;
+ uint64_t def_type;
+};
+
static const struct fixed_range_block {
uint32_t base_msr; /* start address of an MTRR block */
unsigned int ranges; /* number of MTRRs in this block */
@@ -395,9 +400,7 @@ static bool set_mtrr_var_ranges(unsigned int index, struct mtrr_var_range *vr)
return changed;
}

-static uint64_t deftype;
-
-static unsigned long set_mtrr_state(void)
+static unsigned long set_mtrr_state(uint64_t *deftype)
/* [SUMMARY] Set the MTRR state for this CPU.
<state> The MTRR state information to read.
<ctxt> Some relevant CPU context.
@@ -415,14 +418,12 @@ static unsigned long set_mtrr_state(void)
if (mtrr_state.have_fixed && set_fixed_ranges(mtrr_state.fixed_ranges))
change_mask |= MTRR_CHANGE_MASK_FIXED;

- /* Set_mtrr_restore restores the old value of MTRRdefType,
- so to set it we fiddle with the saved value */
- if ((deftype & 0xff) != mtrr_state.def_type
- || MASK_EXTR(deftype, MTRRdefType_E) != mtrr_state.enabled
- || MASK_EXTR(deftype, MTRRdefType_FE) != mtrr_state.fixed_enabled) {
- deftype = (deftype & ~0xcff) | mtrr_state.def_type |
- MASK_INSR(mtrr_state.enabled, MTRRdefType_E) |
- MASK_INSR(mtrr_state.fixed_enabled, MTRRdefType_FE);
+ if ((*deftype & 0xff) != mtrr_state.def_type
+ || MASK_EXTR(*deftype, MTRRdefType_E) != mtrr_state.enabled
+ || MASK_EXTR(*deftype, MTRRdefType_FE) != mtrr_state.fixed_enabled) {
+ *deftype = (*deftype & ~0xcff) | mtrr_state.def_type |
+ MASK_INSR(mtrr_state.enabled, MTRRdefType_E) |
+ MASK_INSR(mtrr_state.fixed_enabled, MTRRdefType_FE);
change_mask |= MTRR_CHANGE_MASK_DEFTYPE;
}

@@ -439,7 +440,7 @@ static DEFINE_SPINLOCK(set_atomicity_lock);
* has been called.
*/

-static bool prepare_set(void)
+static void mtrr_pause_caching(struct mtrr_pausing_state *state)
{
unsigned long cr4;

@@ -461,7 +462,9 @@ static bool prepare_set(void)
alternative("wbinvd", "", X86_FEATURE_XEN_SELFSNOOP);

cr4 = read_cr4();
- if (cr4 & X86_CR4_PGE)
+ state->pge = cr4 & X86_CR4_PGE;
+
+ if (state->pge)
write_cr4(cr4 & ~X86_CR4_PGE);
else if (use_invpcid)
invpcid_flush_all();
@@ -469,27 +472,25 @@ static bool prepare_set(void)
write_cr3(read_cr3());

/* Save MTRR state */
- rdmsrl(MSR_MTRRdefType, deftype);
+ state->def_type = rdmsr(MSR_MTRRdefType);

/* Disable MTRRs, and set the default type to uncached */
- mtrr_wrmsr(MSR_MTRRdefType, deftype & ~0xcff);
+ mtrr_wrmsr(MSR_MTRRdefType, state->def_type & ~0xcff);

/* Again, only flush caches if we have to. */
alternative("wbinvd", "", X86_FEATURE_XEN_SELFSNOOP);
-
- return cr4 & X86_CR4_PGE;
}

-static void post_set(bool pge)
+static void mtrr_resume_caching(struct mtrr_pausing_state state)
{
/* Intel (P6) standard MTRRs */
- mtrr_wrmsr(MSR_MTRRdefType, deftype);
+ mtrr_wrmsr(MSR_MTRRdefType, state.def_type);

/* Enable caches */
write_cr0(read_cr0() & ~X86_CR0_CD);

/* Reenable CR4.PGE (also flushes the TLB) */
- if (pge)
+ if (state.pge)
write_cr4(read_cr4() | X86_CR4_PGE);
else if (use_invpcid)
invpcid_flush_all();
@@ -503,15 +504,15 @@ void mtrr_set_all(void)
{
unsigned long mask, count;
unsigned long flags;
- bool pge;
+ struct mtrr_pausing_state pausing_state;

local_irq_save(flags);
- pge = prepare_set();
+ mtrr_pause_caching(&pausing_state);

/* Actually set the state */
- mask = set_mtrr_state();
+ mask = set_mtrr_state(&pausing_state.def_type);

- post_set(pge);
+ mtrr_resume_caching(pausing_state);
local_irq_restore(flags);

/* Use the atomic bitops to update the global mask */
@@ -536,12 +537,12 @@ void mtrr_set(
{
unsigned long flags;
struct mtrr_var_range *vr;
- bool pge;
+ struct mtrr_pausing_state pausing_state;

vr = &mtrr_state.var_ranges[reg];

local_irq_save(flags);
- pge = prepare_set();
+ mtrr_pause_caching(&pausing_state);

if (size == 0) {
/* The invalid bit is kept in the mask, so we simply clear the
@@ -562,7 +563,7 @@ void mtrr_set(
mtrr_wrmsr(MSR_IA32_MTRR_PHYSMASK(reg), vr->mask);
}

- post_set(pge);
+ mtrr_resume_caching(pausing_state);
local_irq_restore(flags);
}

--
2.55.0

[Sergii Dmytruk]

From: Michał Żygowski <michal....@3mdeb.com>

Report TXT capabilities so that dom0 can query the Intel TXT or AMD
SKINIT support information using xl dmesg.

Signed-off-by: Michał Żygowski <michal....@3mdeb.com>

Signed-off-by: Sergii Dmytruk <sergii....@3mdeb.com>
---

Notes:

v4: fixed conditions for not reporting capabilities (match correct comments)
v4: define GETSEC_* macros used only by xen/arch/x86/cpu/intel.c in the file itself (to not depend on Slaunch)
v4: don't postpone restoring state of X86_CR4_SMXE, do it before printing test results

xen/arch/x86/cpu/amd.c | 16 +++++++++++++

xen/arch/x86/cpu/cpu.h | 1 +
xen/arch/x86/cpu/hygon.c | 1 +

xen/arch/x86/cpu/intel.c | 50 ++++++++++++++++++++++++++++++++++++++++
4 files changed, 68 insertions(+)

diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c
index 70783c9a0a..5ea16ad8a8 100644
--- a/xen/arch/x86/cpu/amd.c
+++ b/xen/arch/x86/cpu/amd.c
@@ -617,6 +617,21 @@ void amd_process_freq(const struct cpuinfo_x86 *c,
*low_mhz = amd_parse_freq(c->family, lo);
}

+void amd_log_skinit(const struct cpuinfo_x86 *c)
+{
+ /*
+ * Run only on BSP and not during resume to report the capability only once.
+ */
+ if ( system_state == SYS_STATE_resume || smp_processor_id() )
+ return;
+
+ printk("CPU: SKINIT capability ");
+ if ( !test_bit(X86_FEATURE_SKINIT, &boot_cpu_data.x86_capability) )
+ printk("not supported\n");
+ else
+ printk("supported\n");
+}
+
void cf_check early_init_amd(struct cpuinfo_x86 *c)
{
if (c == &boot_cpu_data)
@@ -1325,6 +1340,7 @@ static void cf_check init_amd(struct cpuinfo_x86 *c)
setup_force_cpu_cap(X86_FEATURE_XEN_REP_MOVSB);

amd_log_freq(c);
+ amd_log_skinit(c);
}

const struct cpu_dev __initconst_cf_clobber amd_cpu_dev = {
diff --git a/xen/arch/x86/cpu/cpu.h b/xen/arch/x86/cpu/cpu.h
index bbede57ab0..17935190b7 100644
--- a/xen/arch/x86/cpu/cpu.h
+++ b/xen/arch/x86/cpu/cpu.h
@@ -21,6 +21,7 @@ extern bool detect_extended_topology(struct cpuinfo_x86 *c);

void cf_check early_init_amd(struct cpuinfo_x86 *c);
void amd_log_freq(const struct cpuinfo_x86 *c);
+void amd_log_skinit(const struct cpuinfo_x86 *c);
void amd_init_de_cfg(const struct cpuinfo_x86 *c);
void amd_init_lfence_dispatch(void);
void amd_init_ssbd(const struct cpuinfo_x86 *c);
diff --git a/xen/arch/x86/cpu/hygon.c b/xen/arch/x86/cpu/hygon.c
index 7a9fc25d31..608a7c4319 100644
--- a/xen/arch/x86/cpu/hygon.c
+++ b/xen/arch/x86/cpu/hygon.c
@@ -90,6 +90,7 @@ static void cf_check init_hygon(struct cpuinfo_x86 *c)
}

amd_log_freq(c);
+ amd_log_skinit(c);
}

const struct cpu_dev __initconst_cf_clobber hygon_cpu_dev = {
diff --git a/xen/arch/x86/cpu/intel.c b/xen/arch/x86/cpu/intel.c
index 90c9d36186..ddb34c0c02 100644
--- a/xen/arch/x86/cpu/intel.c
+++ b/xen/arch/x86/cpu/intel.c
@@ -14,6 +14,11 @@

#include "cpu.h"

+/* EAX value for GETSEC leaf functions. Intel SDM: GETSEC[CAPABILITIES] */
+#define GETSEC_CAPABILITIES 0
+/* Intel SDM: GETSEC Capability Result Encoding */
+#define GETSEC_CAP_TXT_CHIPSET 1
+
/*
* MSR_MCU_OPT_CTRL is a collection of unrelated functionality, with separate
* enablement requirements, but which want to be consistent across the system.
@@ -620,6 +625,49 @@ static void init_intel_perf(struct cpuinfo_x86 *c)
}
}

+/*
+ * Print out the SMX and TXT capabilties, so that dom0 can determine if the
+ * system is DRTM-capable.
+ */
+static void intel_log_smx_txt(void)
+{
+ unsigned long cr4_val, getsec_caps;
+
+ /*
+ * Run only on BSP and not during resume to report the capability only once.
+ */
+ if ( system_state == SYS_STATE_resume || smp_processor_id() )
+ return;
+
+ printk("CPU: SMX capability ");
+ if ( !test_bit(X86_FEATURE_SMX, &boot_cpu_data.x86_capability) )
+ {
+ printk("not supported\n");
+ return;
+ }
+ printk("supported\n");
+
+ /* Can't run GETSEC without VMX and SMX */
+ if ( !test_bit(X86_FEATURE_VMX, &boot_cpu_data.x86_capability) )
+ return;
+
+ cr4_val = read_cr4();
+ if ( !(cr4_val & X86_CR4_SMXE) )
+ write_cr4(cr4_val | X86_CR4_SMXE);
+
+ asm volatile ("getsec\n"
+ : "=a" (getsec_caps)
+ : "a" (GETSEC_CAPABILITIES), "b" (0) :);
+
+ if ( !(cr4_val & X86_CR4_SMXE) )
+ write_cr4(cr4_val & ~X86_CR4_SMXE);
+
+ if ( getsec_caps & GETSEC_CAP_TXT_CHIPSET )
+ printk("Chipset supports TXT\n");
+ else
+ printk("Chipset does not support TXT\n");
+}
+
static void cf_check init_intel(struct cpuinfo_x86 *c)
{
/* Detect the extended topology information if available */
@@ -634,6 +682,8 @@ static void cf_check init_intel(struct cpuinfo_x86 *c)
detect_ht(c);
}

+ intel_log_smx_txt();
+
/* Work around errata */
Intel_errata_workarounds(c);

--
2.55.0

[Sergii Dmytruk]

From: Krystian Hebel <krystia...@3mdeb.com>

This file is built twice: for early 32b mode without paging and for 64b
code. The expectation is that the data that's measured early is small
and thus sending it to TPM to do the hashing is viable. Version with
paging computes digests and only sends their values to TPM, thus
permitting hashing of large chunks of data like dom0's kernel and
initrd (sending them to TPM would take multiple minutes).

Signed-off-by: Krystian Hebel <krystia...@3mdeb.com>

Signed-off-by: Sergii Dmytruk <sergii....@3mdeb.com>
---

Notes:

v4: renamed from "x86/tpm.c: code for early hashing and extending PCRs (for TPM1.2)"
v4: no longer depends on Slaunch
v4: __EARLY_SLAUNCH__ got replaced with __EARLY_TPM__
v4: fixed SPDX license comments
v4: added short description at the top
v4: TPM_TIS_* => TPM_MMIO_*
v4: tpm_hash_extend() now returns an error code
v4: tpm_hash_extend() now accepts list of hashes like TPM2 but expects at most SHA1
v4: turned is_tpm12() into public tpm_is_tpm1() function (to be used for event log)
v4: added xen/arch/x86/include/asm/tpm1.h with TPM1.2 TCG declarations
v4: removed swap16() and swap32() macros to use macros from <xen/byteorder.h>
v4: no more `static inline` in tpm.c, it's pointless there
v4: style fixes for empty loops, operator placement on wrapped lines, checking for unset bits
v4: take TPM burst count into account
v4: fixed incorrect check for `data_avail` when communicating with TPM
v4: internal functions return TPM error code instead of `bool`
v4: added command and response fields to `union cmd_rsp` to make using it easier
v4: `unsigned` => `unsigned int`
v4: not opencoding ROUNDDOWN() macro
v4: digest storage became optional
v4: returns TPM_INTERNAL_ERROR if not dealing with TPM1.2 or on communication error
v4: the code is written for TIS, but has room for other TPM interfaces

xen/arch/x86/Makefile | 1 +
xen/arch/x86/boot/Makefile | 5 +
xen/arch/x86/include/asm/tpm.h | 69 ++++++
xen/arch/x86/include/asm/tpm1.h | 79 +++++++
xen/arch/x86/tpm.c | 406 ++++++++++++++++++++++++++++++++
5 files changed, 560 insertions(+)

create mode 100644 xen/arch/x86/include/asm/tpm.h
create mode 100644 xen/arch/x86/include/asm/tpm1.h

create mode 100644 xen/arch/x86/tpm.c

diff --git a/xen/arch/x86/Makefile b/xen/arch/x86/Makefile
index b14eca98bf..293f3bee35 100644
--- a/xen/arch/x86/Makefile
+++ b/xen/arch/x86/Makefile
@@ -68,6 +68,7 @@ obj-y += string.o
obj-$(CONFIG_SYSCTL) += sysctl.o
obj-$(CONFIG_TBOOT) += tboot.o
obj-y += time.o
+obj-y += tpm.o
obj-y += traps-setup.o
obj-y += traps.o
obj-$(CONFIG_INTEL) += tsx.o
diff --git a/xen/arch/x86/boot/Makefile b/xen/arch/x86/boot/Makefile
index ff0d61d7ac..feae17c14a 100644
--- a/xen/arch/x86/boot/Makefile
+++ b/xen/arch/x86/boot/Makefile
@@ -5,6 +5,7 @@ obj-bin-y += $(obj64)
obj32 := cmdline.32.o
obj32 += reloc.32.o
obj32 += reloc-trampoline.32.o
+obj32 += tpm-early.32.o

obj64 := reloc-trampoline.o

@@ -28,6 +29,10 @@ $(obj32): XEN_CFLAGS := $(CFLAGS_x86_32) -fpic
$(obj)/%.32.o: $(src)/%.c FORCE
$(call if_changed_rule,cc_o_c)

+$(obj)/tpm-early.32.o: XEN_CFLAGS += -D__EARLY_TPM__
+$(obj)/tpm-early.32.o: $(src)/../tpm.c FORCE
+ $(call if_changed_rule,cc_o_c)
+
orphan-handling-$(call ld-option,--orphan-handling=error) := --orphan-handling=error
LDFLAGS_DIRECT-$(call ld-option,--warn-rwx-segments) := --no-warn-rwx-segments
LDFLAGS_DIRECT += $(LDFLAGS_DIRECT-y)
diff --git a/xen/arch/x86/include/asm/tpm.h b/xen/arch/x86/include/asm/tpm.h
new file mode 100644
index 0000000000..06b54fb786
--- /dev/null
+++ b/xen/arch/x86/include/asm/tpm.h
@@ -0,0 +1,69 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * A TPM driver for both normal and early boot environments.
+ *
+ * Copyright (c) 2022-2026 3mdeb Sp. z o.o. All rights reserved.
+ */
+
+#ifndef X86_TPM_H
+#define X86_TPM_H
+
+#include <xen/types.h>
+
+#define TPM_INTERNAL_ERROR 0xffffffffU
+
+#define TPM_MMIO_BASE 0xfed40000U
+#define TPM_MMIO_SIZE 0x00010000U
+
+/* These are defined for TPM2, but they are used by generic API. */
+#define TPM_ALG_SHA1 0x0004
+#define TPM_ALG_SHA256 0x000b
+#define TPM_ALG_NULL 0x0010
+
+/*
+ * These two structures are for convenience, they don't correspond to anything
+ * in any specification.
+ */
+struct tpm_log_hash {
+ uint16_t alg; /* TPM_ALG_* */
+ uint16_t size;
+ uint8_t *data; /* Non-owning reference to a buffer inside log entry. */
+};
+/* Should be more than enough for now and awhile in the future. */
+#define MAX_TPM_HASH_COUNT 8
+struct tpm_log_hashes {
+ uint32_t count;
+ struct tpm_log_hash hashes[MAX_TPM_HASH_COUNT];
+};
+
+/* All fields of the following structs are big endian. */
+
+struct tpm_cmd_hdr {
+ uint16_t tag;
+ uint32_t paramSize;
+ uint32_t ordinal;
+} __packed;
+
+struct tpm_rsp_hdr {
+ uint16_t tag;
+ uint32_t paramSize;
+ uint32_t returnCode;
+} __packed;
+
+/* Checks whether TPM belongs to TPM 1 family, the only alternative is TPM 2. */
+bool tpm_is_tpm1(void);
+
+/*
+ * The list of hashes must either be empty or contain nothing but SHA1 hash when
+ * tpm_is_tpm1() returns true.
+ *
+ * Returns:
+ * - TPM error code when < 4096 (0 means success)
+ * - TPM_INTERNAL_ERROR on invalid invocation or a failure to communicate with
+ * a TPM device
+ */
+uint32_t tpm_hash_extend(unsigned int loc, unsigned int pcr, const uint8_t *buf,
+ unsigned int size,
+ const struct tpm_log_hashes *log_hashes);
+
+#endif /* X86_TPM_H */
diff --git a/xen/arch/x86/include/asm/tpm1.h b/xen/arch/x86/include/asm/tpm1.h
new file mode 100644
index 0000000000..d1cb2cc041
--- /dev/null
+++ b/xen/arch/x86/include/asm/tpm1.h
@@ -0,0 +1,79 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * TPM1.2-related declarations defined by Trusted Computing Group (TCG).
+ *
+ * Copyright (c) 2022-2026 3mdeb Sp. z o.o. All rights reserved.
+ */
+
+#ifndef X86_TPM1_H
+#define X86_TPM1_H
+
+#include <xen/inttypes.h>
+#include <xen/sha1.h>
+
+#include <asm/tpm.h>
+
+#define TPM_ORD_Extend 0x00000014
+#define TPM_ORD_SHA1Start 0x000000A0
+#define TPM_ORD_SHA1Update 0x000000A1
+#define TPM_ORD_SHA1CompleteExtend 0x000000A3
+
+#define TPM_TAG_RQU_COMMAND 0x00C1
+#define TPM_TAG_RSP_COMMAND 0x00C4
+
+/* All fields of the following structs are big endian. */
+
+struct extend_cmd {
+ struct tpm_cmd_hdr h;
+ uint32_t pcrNum;
+ uint8_t inDigest[SHA1_DIGEST_SIZE];
+} __packed;
+
+struct extend_rsp {
+ struct tpm_rsp_hdr h;
+ uint8_t outDigest[SHA1_DIGEST_SIZE];
+} __packed;
+
+struct sha1_start_cmd {
+ struct tpm_cmd_hdr h;
+} __packed;
+
+struct sha1_start_rsp {
+ struct tpm_rsp_hdr h;
+ uint32_t maxNumBytes;
+} __packed;
+
+struct sha1_update_cmd {
+ struct tpm_cmd_hdr h;
+ uint32_t numBytes; /* Must be a multiple of 64 */
+ uint8_t hashData[];
+} __packed;
+
+struct sha1_update_rsp {
+ struct tpm_rsp_hdr h;
+} __packed;
+
+struct sha1_complete_extend_cmd {
+ struct tpm_cmd_hdr h;
+ uint32_t pcrNum;
+ uint32_t hashDataSize; /* 0-64, inclusive */
+ uint8_t hashData[];
+} __packed;
+
+struct sha1_complete_extend_rsp {
+ struct tpm_rsp_hdr h;
+ uint8_t hashValue[SHA1_DIGEST_SIZE];
+ uint8_t outDigest[SHA1_DIGEST_SIZE];
+} __packed;
+
+/* The structures below are for TPM event log and these are in little-endian. */
+
+struct TPM12_PCREvent {
+ uint32_t PCRIndex;
+ uint32_t Type;
+ uint8_t Digest[SHA1_DIGEST_SIZE];
+ uint32_t Size;
+ uint8_t Data[];
+};
+
+#endif /* X86_TPM1_H */
diff --git a/xen/arch/x86/tpm.c b/xen/arch/x86/tpm.c
new file mode 100644
index 0000000000..9efaf75440
--- /dev/null
+++ b/xen/arch/x86/tpm.c
@@ -0,0 +1,406 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * TPM driver for extending PCRs.
+ *
+ * This file is built twice:
+ * 1. For early 32b mode without paging the code sends data to be hashed to
+ * TPM.
+ * 2. For 64b code which computes hashes and only extends them into PCRs.
+ *
+ * Copyright (c) 2022-2026 3mdeb Sp. z o.o. All rights reserved.
+ */
+
+#include <xen/byteorder.h>
+#include <xen/sha1.h>
+#include <xen/string.h>
+#include <xen/types.h>
+
+#include <asm/tpm.h>
+#include <asm/tpm1.h>
+
+#ifdef __EARLY_TPM__
+
+#include <xen/macros.h>
+
+#ifdef __va
+#error "__va defined in non-paged mode!"
+#endif
+
+#define __va(x) _p(x)
+
+/*
+ * The code is being compiled as a standalone binary without linking to any
+ * other part of Xen. Providing implementation of builtin functions in this
+ * case is necessary if compiler chooses to not use an inline builtin.
+ */
+void *(memcpy)(void *dest, const void *src, size_t n)
+{
+ const uint8_t *s = src;
+ uint8_t *d = dest;
+
+ while ( n-- )
+ *d++ = *s++;
+
+ return dest;
+}
+
+#else /* __EARLY_TPM__ */
+
+#include <xen/mm.h>
+#include <xen/pfn.h>
+
+#endif /* __EARLY_TPM__ */
+
+#define TPM_LOC_REG(loc, reg) (0x1000 * (loc) + (reg))
+
+/******************************** MMIO helpers ********************************/
+
+static uint32_t tpm_read32(unsigned int reg)
+{
+ return *(volatile uint32_t *)__va(TPM_MMIO_BASE + reg);
+}
+
+static uint16_t tpm_read16(unsigned int reg)
+{
+ return *(volatile uint16_t *)__va(TPM_MMIO_BASE + reg);
+}
+
+static uint8_t tpm_read8(unsigned int reg)
+{
+ return *(volatile uint8_t *)__va(TPM_MMIO_BASE + reg);
+}
+
+static void tpm_write8(unsigned int reg, uint8_t val)
+{
+ *(volatile uint8_t *)__va(TPM_MMIO_BASE + reg) = val;
+}
+
+/************************** TIS register definitions **************************/
+
+#define TIS_ACCESS_(x) TPM_LOC_REG(x, 0x00)
+#define ACCESS_REQUEST_USE (1 << 1)
+#define ACCESS_ACTIVE_LOCALITY (1 << 5)
+#define TIS_INTF_CAPABILITY_(x) TPM_LOC_REG(x, 0x14)
+#define INTF_VERSION_MASK 0x70000000
+#define TIS_STS_(x) TPM_LOC_REG(x, 0x18)
+#define STS_FAMILY_MASK 0x0C000000
+#define STS_EXPECT_DATA (1 << 3)
+#define STS_DATA_AVAIL (1 << 4)
+#define STS_TPM_GO (1 << 5)
+#define STS_COMMAND_READY (1 << 6)
+#define STS_VALID (1 << 7)
+#define TIS_BURST_COUNT_(x) TPM_LOC_REG(x, 0x19) /* the middle of STS */
+#define TIS_DATA_FIFO_(x) TPM_LOC_REG(x, 0x24)
+
+/************************** TIS locality & command ****************************/
+
+static void tis_request_locality(unsigned int loc)
+{
+ tpm_write8(TIS_ACCESS_(loc), ACCESS_REQUEST_USE);
+ /* Check that locality was actually activated. */
+ while ( !(tpm_read8(TIS_ACCESS_(loc)) & ACCESS_ACTIVE_LOCALITY) )
+ ;
+}
+
+static void tis_relinquish_locality(unsigned int loc)
+{
+ tpm_write8(TIS_ACCESS_(loc), ACCESS_ACTIVE_LOCALITY);
+}
+
+static uint16_t tis_get_burst_count(unsigned int loc)
+{
+ return tpm_read16(TIS_BURST_COUNT_(loc));
+}
+
+static void tis_send_cmd(unsigned int loc, uint8_t *buf, unsigned int i_size,
+ unsigned int *o_size)
+{
+ /*
+ * Values of "expect data" and "data available" bits count only when "valid"
+ * field is set as well.
+ */
+ const unsigned int expect_data = STS_VALID | STS_EXPECT_DATA;
+ const unsigned int data_avail = STS_VALID | STS_DATA_AVAIL;
+
+ unsigned int i;
+ unsigned int burst_count;
+
+ /* Make sure TPM can accept a command. */
+ if ( !(tpm_read8(TIS_STS_(loc)) & STS_COMMAND_READY) )
+ {
+ /* Abort current command. */
+ tpm_write8(TIS_STS_(loc), STS_COMMAND_READY);
+ /* Wait until TPM is ready for a new one. */
+ while ( !(tpm_read8(TIS_STS_(loc)) & STS_COMMAND_READY) )
+ ;
+ }
+
+ i = 0;
+ while ( i < i_size )
+ {
+ do
+ burst_count = tis_get_burst_count(loc);
+ while ( burst_count == 0 );
+
+ while ( burst_count-- > 0 && i < i_size )
+ tpm_write8(TIS_DATA_FIFO_(loc), buf[i++]);
+
+ if ( i < i_size )
+ {
+ while ( (tpm_read8(TIS_STS_(loc)) & expect_data) != expect_data )
+ ;
+ }
+ }
+
+ tpm_write8(TIS_STS_(loc), STS_TPM_GO);
+
+ /* Wait for the first byte of response. */
+ while ( (tpm_read8(TIS_STS_(loc)) & data_avail) != data_avail )
+ ;
+
+ i = 0;
+ do {
+ do
+ burst_count = tis_get_burst_count(loc);
+ while ( burst_count == 0 );
+
+ while ( burst_count-- > 0 && i < *o_size)
+ buf[i++] = tpm_read8(TIS_DATA_FIFO_(loc));
+
+ while ( !(tpm_read8(TIS_STS_(loc)) & STS_VALID) )
+ ;
+ } while ( i < *o_size &&
+ (tpm_read8(TIS_STS_(loc)) & data_avail) == data_avail );
+
+ *o_size = i;
+
+ tpm_write8(TIS_STS_(loc), STS_COMMAND_READY);
+}
+
+/************************** Interface dispatch ********************************/
+
+static void request_locality(unsigned int loc)
+{
+ tis_request_locality(loc);
+}
+
+static void relinquish_locality(unsigned int loc)
+{
+ tis_relinquish_locality(loc);
+}
+
+static void send_cmd(unsigned int loc, uint8_t *buf, unsigned int i_size,
+ unsigned int *o_size)
+{
+ tis_send_cmd(loc, buf, i_size, o_size);
+}
+
+bool tpm_is_tpm1(void)
+{
+ uint32_t intf_version;
+
+ /*
+ * If one of these conditions is true:
+ * - INTF_CAPABILITY_x.interfaceVersion is 0 (TIS <= 1.21)
+ * - INTF_CAPABILITY_x.interfaceVersion is 2 (TIS == 1.3)
+ * - STS_x.tpmFamily is 0
+ * we're dealing with TPM1.2.
+ */
+ intf_version = tpm_read32(TIS_INTF_CAPABILITY_(0)) & INTF_VERSION_MASK;
+ return (intf_version == 0x00000000 || intf_version == 0x20000000 ||
+ !(tpm_read32(TIS_STS_(0)) & STS_FAMILY_MASK));
+}
+
+/****************************** TPM1.2 specific *******************************/
+
+#ifdef __EARLY_TPM__
+/*
+ * TPM1.2 is required to support commands of up to 1101 bytes, vendors rarely
+ * go above that. Limit maximum size of block of data to be hashed to 1024.
+ */
+#define MAX_HASH_BLOCK 1024
+#define CMD_RSP_BUF_SIZE (sizeof(struct sha1_update_cmd) + MAX_HASH_BLOCK)
+
+union cmd_rsp {
+ struct tpm_cmd_hdr c;
+ struct tpm_rsp_hdr r;
+ struct sha1_start_cmd start_c;
+ struct sha1_start_rsp start_r;
+ struct sha1_update_cmd update_c;
+ struct sha1_update_rsp update_r;
+ struct sha1_complete_extend_cmd finish_c;
+ struct sha1_complete_extend_rsp finish_r;
+ uint8_t buf[CMD_RSP_BUF_SIZE];
+};
+
+static uint32_t tpm12_hash_extend(unsigned int loc, const uint8_t *buf,
+ unsigned int size, unsigned int pcr,
+ const struct tpm_log_hashes *log_hashes)
+{
+ union cmd_rsp cmd_rsp;
+ unsigned int max_bytes = MAX_HASH_BLOCK;
+ unsigned int o_size = sizeof(cmd_rsp);
+ uint32_t rc;
+
+ request_locality(loc);
+
+ cmd_rsp.start_c = (struct sha1_start_cmd) {
+ .h.tag = cpu_to_be16(TPM_TAG_RQU_COMMAND),
+ .h.paramSize = cpu_to_be32(sizeof(cmd_rsp.start_c)),
+ .h.ordinal = cpu_to_be32(TPM_ORD_SHA1Start),
+ };
+
+ send_cmd(loc, cmd_rsp.buf, be32_to_cpu(cmd_rsp.c.paramSize), &o_size);
+ if ( o_size < sizeof(cmd_rsp.start_r) )
+ {
+ rc = TPM_INTERNAL_ERROR;
+ goto error;
+ }
+ rc = be32_to_cpu(cmd_rsp.r.returnCode);
+ if ( rc != 0 )
+ goto error;
+
+ if ( max_bytes > be32_to_cpu(cmd_rsp.start_r.maxNumBytes) )
+ max_bytes = be32_to_cpu(cmd_rsp.start_r.maxNumBytes);
+
+ while ( size > 64 )
+ {
+ if ( size < max_bytes )
+ max_bytes = ROUNDDOWN(size, 64);
+
+ o_size = sizeof(cmd_rsp);
+
+ cmd_rsp.update_c = (struct sha1_update_cmd) {
+ .h.tag = cpu_to_be16(TPM_TAG_RQU_COMMAND),
+ .h.paramSize = cpu_to_be32(sizeof(cmd_rsp.update_c) + max_bytes),
+ .h.ordinal = cpu_to_be32(TPM_ORD_SHA1Update),
+ .numBytes = cpu_to_be32(max_bytes),
+ };
+ memcpy(cmd_rsp.update_c.hashData, buf, max_bytes);
+
+ send_cmd(loc, cmd_rsp.buf, be32_to_cpu(cmd_rsp.c.paramSize), &o_size);
+ if ( o_size < sizeof(cmd_rsp.update_r) )
+ {
+ rc = TPM_INTERNAL_ERROR;
+ goto error;
+ }
+ rc = be32_to_cpu(cmd_rsp.r.returnCode);
+ if ( rc != 0 )
+ goto error;
+
+ size -= max_bytes;
+ buf += max_bytes;
+ }
+
+ o_size = sizeof(cmd_rsp);
+
+ cmd_rsp.finish_c = (struct sha1_complete_extend_cmd) {
+ .h.tag = cpu_to_be16(TPM_TAG_RQU_COMMAND),
+ .h.paramSize = cpu_to_be32(sizeof(cmd_rsp.finish_c) + size),
+ .h.ordinal = cpu_to_be32(TPM_ORD_SHA1CompleteExtend),
+ .pcrNum = cpu_to_be32(pcr),
+ .hashDataSize = cpu_to_be32(size),
+ };
+ memcpy(cmd_rsp.finish_c.hashData, buf, size);
+
+ send_cmd(loc, cmd_rsp.buf, be32_to_cpu(cmd_rsp.c.paramSize), &o_size);
+ if ( o_size < sizeof(cmd_rsp.finish_r) )
+ {
+ rc = TPM_INTERNAL_ERROR;
+ goto error;
+ }
+ rc = be32_to_cpu(cmd_rsp.r.returnCode);
+ if ( rc != 0 )
+ goto error;
+
+ if ( log_hashes->count != 0 )
+ {
+ memcpy(log_hashes->hashes[0].data, cmd_rsp.finish_r.hashValue,
+ SHA1_DIGEST_SIZE);
+ }
+
+ rc = 0;
+
+ error:
+ relinquish_locality(loc);
+ return rc;
+}
+
+#else
+
+union cmd_rsp {
+ struct tpm_cmd_hdr c;
+ struct tpm_rsp_hdr r;
+ struct extend_cmd extend_c;
+ struct extend_rsp extend_r;
+};
+
+static uint32_t tpm12_hash_extend(unsigned int loc, const uint8_t *buf,
+ unsigned int size, unsigned int pcr,
+ const struct tpm_log_hashes *log_hashes)
+{
+ union cmd_rsp cmd_rsp;
+ unsigned int o_size = sizeof(cmd_rsp);
+ uint32_t rc;
+
+ request_locality(loc);
+
+ cmd_rsp.extend_c = (struct extend_cmd) {
+ .h.tag = cpu_to_be16(TPM_TAG_RQU_COMMAND),
+ .h.paramSize = cpu_to_be32(sizeof(cmd_rsp.extend_c)),
+ .h.ordinal = cpu_to_be32(TPM_ORD_Extend),
+ .pcrNum = cpu_to_be32(pcr),
+ };
+
+ sha1(cmd_rsp.extend_c.inDigest, buf, size);
+ if ( log_hashes->count != 0 )
+ {
+ memcpy(log_hashes->hashes[0].data, cmd_rsp.extend_c.inDigest,
+ SHA1_DIGEST_SIZE);
+ }
+
+ send_cmd(loc, (uint8_t *)&cmd_rsp, be32_to_cpu(cmd_rsp.c.paramSize),
+ &o_size);
+ if ( o_size < sizeof(cmd_rsp.extend_r) )
+ {
+ rc = TPM_INTERNAL_ERROR;
+ goto error;
+ }
+ rc = be32_to_cpu(cmd_rsp.r.returnCode);
+ if ( rc != 0 )
+ goto error;
+
+ relinquish_locality(loc);
+
+ rc = 0;
+
+ error:
+ return rc;
+}
+
+#endif /* __EARLY_TPM__ */
+
+/************************** end of TPM1.2 specific ****************************/
+
+uint32_t tpm_hash_extend(unsigned int loc, unsigned int pcr, const uint8_t *buf,
+ unsigned int size,
+ const struct tpm_log_hashes *log_hashes)
+{
+ if ( tpm_is_tpm1() )
+ {
+ if (log_hashes->count != 0 &&
+ !(log_hashes->count == 1 &&
+ log_hashes->hashes[0].alg == TPM_ALG_SHA1 &&
+ log_hashes->hashes[0].size == SHA1_DIGEST_SIZE))
+ {
+#ifndef __EARLY_TPM__
+ printk(XENLOG_ERR "Bad TPM1 log hash for PCR-%u\n", pcr);
+#endif
+ return TPM_INTERNAL_ERROR;
+ }
+
+ return tpm12_hash_extend(loc, buf, size, pcr, log_hashes);
+ }
+
+ return TPM_INTERNAL_ERROR;
+}
--
2.55.0

[Sergii Dmytruk]

SHA1 and SHA256 are hard-coded here, but their support by the TPM is
checked.

CRB isn't supported, only TPM1.2-like TIS interface is (data is passed
via writes and reads to/from a single-byte FIFO register).

Signed-off-by: Sergii Dmytruk <sergii....@3mdeb.com>
Signed-off-by: Szymon Acedański <ac...@invisiblethingslab.com>
Assisted-by: Claude:claude-opus-4-6

Signed-off-by: Sergii Dmytruk <sergii....@3mdeb.com>
---

Notes:

v4: was called "x86/tpm.c: support extending PCRs of TPM2.0"
v4: adds xen/arch/x86/include/asm/tpm2.h with TPM2.0 declarations by TCG
v4: detect CRB and do nothing (implemented separately)
v4: put SPDX license comment on its own line

v4: `unsigned` => `unsigned int`

v4: replace uses of `swap16()` and `swap32()`
v4: more error checks when parsing TPM responses
v4: style fixes for `goto` labels and spacing

xen/arch/x86/include/asm/tpm.h | 5 +
xen/arch/x86/include/asm/tpm2.h | 150 ++++++++++++++
xen/arch/x86/tpm.c | 340 +++++++++++++++++++++++++++++++-
3 files changed, 489 insertions(+), 6 deletions(-)
create mode 100644 xen/arch/x86/include/asm/tpm2.h

diff --git a/xen/arch/x86/include/asm/tpm.h b/xen/arch/x86/include/asm/tpm.h
index 06b54fb786..5fa883dad8 100644
--- a/xen/arch/x86/include/asm/tpm.h
+++ b/xen/arch/x86/include/asm/tpm.h
@@ -57,6 +57,11 @@ bool tpm_is_tpm1(void);

* The list of hashes must either be empty or contain nothing but SHA1 hash when

* tpm_is_tpm1() returns true.
*
+ * When tpm_is_tpm1() returns false, the list of digests can also be used to
+ * determine which hashes to extend. The only hashes that are guaranteed to be
+ * supported are SHA1 and SHA256, all other digests need to be pre-filled by
+ * the caller with some placeholder value.
+ *
* Returns:

* - TPM error code when < 4096 (0 means success)

* - TPM_INTERNAL_ERROR on invalid invocation or a failure to communicate with

diff --git a/xen/arch/x86/include/asm/tpm2.h b/xen/arch/x86/include/asm/tpm2.h
new file mode 100644
index 0000000000..4565d302f3
--- /dev/null
+++ b/xen/arch/x86/include/asm/tpm2.h
@@ -0,0 +1,150 @@

+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*

+ * TPM2.0-related definitions defined by Trusted Computing Group (TCG).

+ *
+ * Copyright (c) 2022-2026 3mdeb Sp. z o.o. All rights reserved.
+ */
+

+#ifndef X86_TPM2_H
+#define X86_TPM2_H
+
+#include <xen/inttypes.h>
+
+#include <asm/tpm.h>
+
+/*
+ * These constants are for TPM2.0 but don't have a distinct prefix to match
+ * names in the specification.
+ */
+
+#define TPM_HT_PCR 0x00
+
+#define TPM_RH_NULL 0x40000007
+#define TPM_RS_PW 0x40000009
+
+#define HR_SHIFT 24
+#define HR_PCR (TPM_HT_PCR << HR_SHIFT)
+
+#define TPM_ST_NO_SESSIONS 0x8001
+#define TPM_ST_SESSIONS 0x8002
+
+#define TPM2_PCR_Extend 0x00000182
+#define TPM2_PCR_HashSequenceStart 0x00000186
+#define TPM2_PCR_SequenceUpdate 0x0000015C
+#define TPM2_PCR_EventSequenceComplete 0x00000185

+
+/* All fields of the following structs are big endian. */
+

+struct tpm2_session_header {
+ uint32_t handle;
+ uint16_t nonceSize;
+ uint8_t nonce[0];
+ uint8_t attrs;
+ uint16_t hmacSize;
+ uint8_t hmac[0];
+} __packed;
+
+struct tpm2_extend_cmd {
+ struct tpm_cmd_hdr h;
+ uint32_t pcrHandle;
+ uint32_t sessionHdrSize;
+ struct tpm2_session_header pcrSession;
+ uint32_t hashCount;
+ uint8_t hashes[0];
+} __packed;
+
+struct tpm2_extend_rsp {

+ struct tpm_rsp_hdr h;
+} __packed;
+

+struct tpm2_sequence_start_cmd {
+ struct tpm_cmd_hdr h;
+ uint16_t hmacSize;
+ uint8_t hmac[0];
+ uint16_t hashAlg;
+} __packed;
+
+struct tpm2_sequence_start_rsp {
+ struct tpm_rsp_hdr h;
+ uint32_t sequenceHandle;
+} __packed;
+
+struct tpm2_sequence_update_cmd {
+ struct tpm_cmd_hdr h;
+ uint32_t sequenceHandle;
+ uint32_t sessionHdrSize;
+ struct tpm2_session_header session;
+ uint16_t dataSize;
+ uint8_t data[0];
+} __packed;
+
+struct tpm2_sequence_update_rsp {

+ struct tpm_rsp_hdr h;
+} __packed;
+

+struct tpm2_sequence_complete_cmd {
+ struct tpm_cmd_hdr h;
+ uint32_t pcrHandle;
+ uint32_t sequenceHandle;
+ uint32_t sessionHdrSize;
+ struct tpm2_session_header pcrSession;
+ struct tpm2_session_header sequenceSession;
+ uint16_t dataSize;
+ uint8_t data[0];
+} __packed;
+
+struct tpm2_sequence_complete_rsp {
+ struct tpm_rsp_hdr h;
+ uint32_t paramSize;
+ uint32_t hashCount;
+ uint8_t hashes[0];
+ /*
+ * Each hash is represented as:
+ * struct {
+ * uint16_t hashAlg;
+ * uint8_t hash[size of hashAlg];
+ * };
+ */

+} __packed;
+
+/* The structures below are for TPM event log and these are in little-endian. */
+

+struct tpm2_pcr_event_header {
+ uint32_t pcrIndex;
+ uint32_t eventType;
+ uint32_t digestCount;
+ uint8_t digests[0];
+ /*
+ * Each hash is represented as:
+ * struct {
+ * uint16_t hashAlg;
+ * uint8_t hash[size of hashAlg];
+ * };
+ */
+ /* uint32_t eventSize; */
+ /* uint8_t event[0]; */
+} __packed;
+
+struct tpm2_digest_sizes {
+ uint16_t algId;
+ uint16_t digestSize;
+} __packed;
+
+struct tpm2_spec_id_event {
+ uint32_t pcrIndex;
+ uint32_t eventType;
+ uint8_t digest[20];
+ uint32_t eventSize;
+ uint8_t signature[16];
+ uint32_t platformClass;
+ uint8_t specVersionMinor;
+ uint8_t specVersionMajor;
+ uint8_t specErrata;
+ uint8_t uintnSize;
+ uint32_t digestCount;
+ struct tpm2_digest_sizes digestSizes[0]; /* variable number of members */
+ /* uint8_t vendorInfoSize; */
+ /* uint8_t vendorInfo[vendorInfoSize]; */
+} __packed;
+
+#endif /* X86_TPM2_H */
diff --git a/xen/arch/x86/tpm.c b/xen/arch/x86/tpm.c
index 9efaf75440..59bb1ff2c4 100644
--- a/xen/arch/x86/tpm.c
+++ b/xen/arch/x86/tpm.c
@@ -12,11 +12,13 @@

#include <xen/byteorder.h>
#include <xen/sha1.h>
+#include <xen/sha2.h>
#include <xen/string.h>
#include <xen/types.h>

#include <asm/tpm.h>
#include <asm/tpm1.h>
+#include <asm/tpm2.h>

#ifdef __EARLY_TPM__

@@ -75,6 +77,22 @@ static void tpm_write8(unsigned int reg, uint8_t val)

*(volatile uint8_t *)__va(TPM_MMIO_BASE + reg) = val;
}

+/************************** Interface detection *******************************/
+
+#define TPM_INTF_ID_(x) TPM_LOC_REG(x, 0x30)
+#define INTF_TYPE_MASK 0x0000000fU
+#define INTF_TYPE_TIS 0x00
+#define INTF_TYPE_CRB 0x01
+
+/*
+ * No static caching: the early 32-bit binary (tpm_early.bin) is built with
+ * "objcopy -j .text", which omits .bss/.data.
+ */
+static bool tpm_is_crb(void)
+{
+ return (tpm_read32(TPM_INTF_ID_(0)) & INTF_TYPE_MASK) == INTF_TYPE_CRB;
+}
+
/************************** TIS register definitions **************************/

#define TIS_ACCESS_(x) TPM_LOC_REG(x, 0x00)
@@ -181,24 +199,37 @@ static void tis_send_cmd(unsigned int loc, uint8_t *buf, unsigned int i_size,

static void request_locality(unsigned int loc)
{
- tis_request_locality(loc);
+ if ( tpm_is_crb() )
+ return;
+ else
+ tis_request_locality(loc);
}

static void relinquish_locality(unsigned int loc)
{
- tis_relinquish_locality(loc);
+ if ( tpm_is_crb() )
+ return;
+ else
+ tis_relinquish_locality(loc);

}

static void send_cmd(unsigned int loc, uint8_t *buf, unsigned int i_size,

unsigned int *o_size)
{
- tis_send_cmd(loc, buf, i_size, o_size);
+ if ( tpm_is_crb() )
+ *o_size = 0;
+ else

+ tis_send_cmd(loc, buf, i_size, o_size);
}

bool tpm_is_tpm1(void)
{
uint32_t intf_version;

+ /* CRB interface is always TPM 2.0. */
+ if ( tpm_is_crb() )
+ return false;
+
/*

* If one of these conditions is true:

* - INTF_CAPABILITY_x.interfaceVersion is 0 (TIS <= 1.21)

@@ -211,14 +242,19 @@ bool tpm_is_tpm1(void)
!(tpm_read32(TIS_STS_(0)) & STS_FAMILY_MASK));
}

-/****************************** TPM1.2 specific *******************************/
+/****************************** TPM1.2 & TPM2.0 *******************************/

-#ifdef __EARLY_TPM__
/*

* TPM1.2 is required to support commands of up to 1101 bytes, vendors rarely

* go above that. Limit maximum size of block of data to be hashed to 1024.
+ *

+ * TPM2.0 should support hashing of at least 1024 bytes.
*/
#define MAX_HASH_BLOCK 1024

+
+/****************************** TPM1.2 specific *******************************/
+
+#ifdef __EARLY_TPM__

#define CMD_RSP_BUF_SIZE (sizeof(struct sha1_update_cmd) + MAX_HASH_BLOCK)

union cmd_rsp {
@@ -382,6 +418,298 @@ static uint32_t tpm12_hash_extend(unsigned int loc, const uint8_t *buf,

/************************** end of TPM1.2 specific ****************************/

+/****************************** TPM2.0 specific *******************************/
+
+#ifdef __EARLY_TPM__
+
+union tpm2_cmd_rsp {
+ uint8_t b[sizeof(struct tpm2_sequence_update_cmd) + MAX_HASH_BLOCK];

+ struct tpm_cmd_hdr c;
+ struct tpm_rsp_hdr r;

+ struct tpm2_sequence_start_cmd start_c;
+ struct tpm2_sequence_start_rsp start_r;
+ struct tpm2_sequence_update_cmd update_c;
+ struct tpm2_sequence_update_rsp update_r;
+ struct tpm2_sequence_complete_cmd finish_c;
+ struct tpm2_sequence_complete_rsp finish_r;
+};
+
+static uint32_t tpm2_hash_extend(unsigned int loc, const uint8_t *buf,

+ unsigned int size, unsigned int pcr,
+ const struct tpm_log_hashes *log_hashes)
+{

+ uint32_t seq_handle;

+ unsigned int max_bytes = MAX_HASH_BLOCK;
+

+ union tpm2_cmd_rsp cmd_rsp;
+ unsigned int o_size;
+ unsigned int i;
+ uint8_t *p;
+ uint32_t rc;
+
+ cmd_rsp.start_c = (struct tpm2_sequence_start_cmd) {
+ .h.tag = cpu_to_be16(TPM_ST_NO_SESSIONS),
+ .h.paramSize = cpu_to_be32(sizeof(cmd_rsp.start_c)),
+ .h.ordinal = cpu_to_be32(TPM2_PCR_HashSequenceStart),
+ /* Compute all supported hashes. */
+ .hashAlg = cpu_to_be16(TPM_ALG_NULL),
+ };
+
+ request_locality(loc);
+
+ o_size = sizeof(cmd_rsp);
+ send_cmd(loc, cmd_rsp.b, be32_to_cpu(cmd_rsp.c.paramSize), &o_size);
+
+ if ( o_size < sizeof(struct tpm_rsp_hdr) )

+ {
+ rc = TPM_INTERNAL_ERROR;
+ goto error;
+ }
+ rc = be32_to_cpu(cmd_rsp.r.returnCode);
+ if ( rc != 0 )
+ goto error;
+

+ seq_handle = be32_to_cpu(cmd_rsp.start_r.sequenceHandle);

+
+ while ( size > 64 )
+ {
+ if ( size < max_bytes )
+ max_bytes = ROUNDDOWN(size, 64);
+

+ cmd_rsp.update_c = (struct tpm2_sequence_update_cmd) {
+ .h.tag = cpu_to_be16(TPM_ST_SESSIONS),

+ .h.paramSize = cpu_to_be32(sizeof(cmd_rsp.update_c) + max_bytes),

+ .h.ordinal = cpu_to_be32(TPM2_PCR_SequenceUpdate),
+ .sequenceHandle = cpu_to_be32(seq_handle),
+ .sessionHdrSize = cpu_to_be32(sizeof(struct tpm2_session_header)),
+ .session.handle = cpu_to_be32(TPM_RS_PW),
+ .dataSize = cpu_to_be16(max_bytes),
+ };
+
+ memcpy(cmd_rsp.update_c.data, buf, max_bytes);

+
+ o_size = sizeof(cmd_rsp);

+ send_cmd(loc, cmd_rsp.b, be32_to_cpu(cmd_rsp.c.paramSize), &o_size);
+
+ if ( o_size < sizeof(struct tpm_rsp_hdr) )

+ {
+ rc = TPM_INTERNAL_ERROR;
+ goto error;
+ }
+ rc = be32_to_cpu(cmd_rsp.r.returnCode);
+ if ( rc != 0 )
+ goto error;
+
+ size -= max_bytes;
+ buf += max_bytes;
+ }
+

+ cmd_rsp.finish_c = (struct tpm2_sequence_complete_cmd) {
+ .h.tag = cpu_to_be16(TPM_ST_SESSIONS),

+ .h.paramSize = cpu_to_be32(sizeof(cmd_rsp.finish_c) + size),

+ .h.ordinal = cpu_to_be32(TPM2_PCR_EventSequenceComplete),
+ .pcrHandle = cpu_to_be32(HR_PCR + pcr),
+ .sequenceHandle = cpu_to_be32(seq_handle),
+ .sessionHdrSize = cpu_to_be32(sizeof(struct tpm2_session_header) * 2),
+ .pcrSession.handle = cpu_to_be32(TPM_RS_PW),
+ .sequenceSession.handle = cpu_to_be32(TPM_RS_PW),
+ .dataSize = cpu_to_be16(size),
+ };
+
+ memcpy(cmd_rsp.finish_c.data, buf, size);

+
+ o_size = sizeof(cmd_rsp);

+ send_cmd(loc, cmd_rsp.b, be32_to_cpu(cmd_rsp.c.paramSize), &o_size);
+
+ if ( o_size < sizeof(struct tpm_rsp_hdr) )

+ {
+ rc = TPM_INTERNAL_ERROR;
+ goto error;
+ }
+ rc = be32_to_cpu(cmd_rsp.r.returnCode);
+ if ( rc != 0 )
+ goto error;
+

+ if ( o_size < sizeof(cmd_rsp.finish_r) )
+ {
+ rc = TPM_INTERNAL_ERROR;
+ goto error;
+ }
+

+ p = cmd_rsp.finish_r.hashes;
+ for ( i = 0; i < be32_to_cpu(cmd_rsp.finish_r.hashCount); ++i )
+ {
+ unsigned int j;
+ uint16_t hash_type;
+
+ if ( p + sizeof(uint16_t) > cmd_rsp.b + o_size )

+ {
+ rc = TPM_INTERNAL_ERROR;
+ goto error;
+ }

+ hash_type = be16_to_cpu(*(uint16_t *)p);
+ p += sizeof(uint16_t);
+
+ for ( j = 0; j < log_hashes->count; ++j )
+ {
+ const struct tpm_log_hash *hash = &log_hashes->hashes[j];
+ if ( hash->alg == hash_type )
+ {
+ if ( p + hash->size > cmd_rsp.b + o_size )

+ {
+ rc = TPM_INTERNAL_ERROR;
+ goto error;
+ }

+ memcpy(hash->data, p, hash->size);
+ p += hash->size;
+ break;
+ }
+ }
+
+ if ( j == log_hashes->count )
+ /* Can't continue parsing without knowing hash size. */
+ break;

+ }
+
+ rc = 0;
+
+ error:
+ relinquish_locality(loc);
+ return rc;
+}
+
+#else
+

+union tpm2_cmd_rsp {
+ /* Enough space for multiple hashes. */
+ uint8_t b[sizeof(struct tpm2_extend_cmd) + 1024];

+ struct tpm_cmd_hdr c;
+ struct tpm_rsp_hdr r;

+ struct tpm2_extend_cmd extend_c;
+ struct tpm2_extend_rsp extend_r;
+};
+
+static uint32_t tpm20_pcr_extend(unsigned int loc, uint32_t pcr_handle,

+ const struct tpm_log_hashes *log_hashes)
+{

+ union tpm2_cmd_rsp cmd_rsp;
+ unsigned int o_size;
+ unsigned int i;
+ uint8_t *p;
+
+ cmd_rsp.extend_c = (struct tpm2_extend_cmd) {
+ .h.tag = cpu_to_be16(TPM_ST_SESSIONS),
+ .h.ordinal = cpu_to_be32(TPM2_PCR_Extend),
+ .pcrHandle = cpu_to_be32(pcr_handle),
+ .sessionHdrSize = cpu_to_be32(sizeof(struct tpm2_session_header)),
+ .pcrSession.handle = cpu_to_be32(TPM_RS_PW),
+ .hashCount = cpu_to_be32(log_hashes->count),
+ };
+
+ p = cmd_rsp.extend_c.hashes;
+ for ( i = 0; i < log_hashes->count; ++i )
+ {
+ const struct tpm_log_hash *hash = &log_hashes->hashes[i];
+
+ if ( p + sizeof(uint16_t) + hash->size > &cmd_rsp.b[sizeof(cmd_rsp)] )
+ {
+ printk(XENLOG_ERR "Hit TPM message size implementation limit: %ld\n",
+ sizeof(cmd_rsp));

+ return TPM_INTERNAL_ERROR;
+ }
+

+ *(uint16_t *)p = cpu_to_be16(hash->alg);
+ p += sizeof(uint16_t);
+
+ memcpy(p, hash->data, hash->size);
+ p += hash->size;
+ }
+
+ /* Fill in command size (size of the whole buffer). */
+ cmd_rsp.c.paramSize = cpu_to_be32(sizeof(cmd_rsp.extend_c) +
+ (p - cmd_rsp.extend_c.hashes));

+
+ o_size = sizeof(cmd_rsp);

+ send_cmd(loc, cmd_rsp.b, be32_to_cpu(cmd_rsp.c.paramSize), &o_size);
+
+ return be32_to_cpu(cmd_rsp.r.returnCode);
+}
+
+static bool tpm2_supports_hash(unsigned int loc,
+ const struct tpm_log_hash *hash)
+{
+ uint32_t rc;
+ struct tpm_log_hashes hashes = {
+ .count = 1,
+ .hashes[0] = *hash,
+ };
+
+ /*
+ * This is a valid way of checking hash support, using it to not implement
+ * TPM2_GetCapability().
+ */
+ rc = tpm20_pcr_extend(loc, /*pcr_handle=*/TPM_RH_NULL, &hashes);
+
+ return rc == 0;
+}
+
+static uint32_t tpm2_hash_extend(unsigned int loc, const uint8_t *buf,

+ unsigned int size, unsigned int pcr,
+ const struct tpm_log_hashes *log_hashes)
+{

+ uint32_t rc;
+ unsigned int i;
+ struct tpm_log_hashes supported_hashes = {0};
+
+ request_locality(loc);
+
+ for ( i = 0; i < log_hashes->count; ++i )
+ {
+ const struct tpm_log_hash *hash = &log_hashes->hashes[i];
+ if ( !tpm2_supports_hash(loc, hash) )
+ {
+ printk(XENLOG_WARNING "Skipped hash unsupported by TPM: %d\n",
+ hash->alg);
+ continue;
+ }
+
+ if ( hash->alg == TPM_ALG_SHA1 )
+ {
+ sha1(hash->data, buf, size);
+ }
+ else if ( hash->alg == TPM_ALG_SHA256 )
+ {
+ sha2_256(hash->data, buf, size);
+ }
+ else
+ {
+ /*
+ * Assuming the caller has initialized the digest with some
+ * pattern.
+ */
+ }
+
+ if ( supported_hashes.count == MAX_TPM_HASH_COUNT )
+ {
+ printk(XENLOG_ERR "Hit hash count implementation limit: %d\n",
+ MAX_TPM_HASH_COUNT);

+ return TPM_INTERNAL_ERROR;
+ }
+

+ supported_hashes.hashes[supported_hashes.count] = *hash;
+ ++supported_hashes.count;
+ }
+
+ rc = tpm20_pcr_extend(loc, HR_PCR + pcr, &supported_hashes);
+ relinquish_locality(loc);
+

+ return rc;
+}
+
+#endif /* __EARLY_TPM__ */
+

+/************************** end of TPM2.0 specific ****************************/
+

uint32_t tpm_hash_extend(unsigned int loc, unsigned int pcr, const uint8_t *buf,

unsigned int size,
const struct tpm_log_hashes *log_hashes)
@@ -402,5 +730,5 @@ uint32_t tpm_hash_extend(unsigned int loc, unsigned int pcr, const uint8_t *buf,

return tpm12_hash_extend(loc, buf, size, pcr, log_hashes);
}

- return TPM_INTERNAL_ERROR;
+ return tpm2_hash_extend(loc, buf, size, pcr, log_hashes);
}
--
2.55.0

[Sergii Dmytruk]

From: Szymon Acedański <ac...@mimuw.edu.pl>

TIS is an older and slower byte-oriented TPM interface that gets
replaced by CRB on modern systems.

Signed-off-by: Szymon Acedański <ac...@invisiblethingslab.com>
Assisted-by: Claude:claude-opus-4-6
Signed-off-by: Sergii Dmytruk <sergii....@3mdeb.com>
---

Notes:

v4: new commit to support CRB interface of TPM2.0

xen/arch/x86/tpm.c | 134 ++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 131 insertions(+), 3 deletions(-)

diff --git a/xen/arch/x86/tpm.c b/xen/arch/x86/tpm.c
index 59bb1ff2c4..a3d9a0d3e5 100644
--- a/xen/arch/x86/tpm.c
+++ b/xen/arch/x86/tpm.c
@@ -72,6 +72,11 @@ static uint8_t tpm_read8(unsigned int reg)
return *(volatile uint8_t *)__va(TPM_MMIO_BASE + reg);
}

+static void tpm_write32(unsigned int reg, uint32_t val)
+{
+ *(volatile uint32_t *)__va(TPM_MMIO_BASE + reg) = val;
+}
+

static void tpm_write8(unsigned int reg, uint8_t val)
{
*(volatile uint8_t *)__va(TPM_MMIO_BASE + reg) = val;

@@ -110,6 +115,31 @@ static bool tpm_is_crb(void)

#define TIS_BURST_COUNT_(x) TPM_LOC_REG(x, 0x19) /* the middle of STS */

#define TIS_DATA_FIFO_(x) TPM_LOC_REG(x, 0x24)

+/************************** CRB register definitions **************************/
+
+#define CRB_LOC_STATE_(x) TPM_LOC_REG(x, 0x00)
+#define CRB_LOC_STATE_LOC_ASSIGNED (1 << 1)
+#define CRB_LOC_STATE_REG_VALID_STS (1 << 7)
+#define CRB_LOC_CTRL_(x) TPM_LOC_REG(x, 0x08)
+#define CRB_LOC_CTRL_REQUEST_ACCESS (1 << 0)
+#define CRB_LOC_CTRL_RELINQUISH (1 << 1)
+#define CRB_CTRL_REQ_(x) TPM_LOC_REG(x, 0x40)
+#define CRB_CTRL_REQ_CMD_READY (1 << 0)
+#define CRB_CTRL_REQ_GO_IDLE (1 << 1)
+#define CRB_CTRL_STS_(x) TPM_LOC_REG(x, 0x44)
+#define CRB_CTRL_STS_ERROR (1 << 0)
+#define CRB_CTRL_CANCEL_(x) TPM_LOC_REG(x, 0x48)
+#define CRB_CTRL_CANCEL_INVOKE (1 << 0)
+#define CRB_CTRL_START_(x) TPM_LOC_REG(x, 0x4C)
+#define CRB_CTRL_START_INVOKE (1 << 0)
+#define CRB_CTRL_CMD_SIZE_(x) TPM_LOC_REG(x, 0x58)
+#define CRB_CTRL_CMD_LADDR_(x) TPM_LOC_REG(x, 0x5C)
+#define CRB_CTRL_CMD_HADDR_(x) TPM_LOC_REG(x, 0x60)
+#define CRB_CTRL_RSP_SIZE_(x) TPM_LOC_REG(x, 0x64)
+#define CRB_CTRL_RSP_ADDR_(x) TPM_LOC_REG(x, 0x68)
+#define CRB_DATA_BUFFER_(x) TPM_LOC_REG(x, 0x80)
+#define CRB_DATA_BUFFER_SIZE 0x0F80
+

/************************** TIS locality & command ****************************/

static void tis_request_locality(unsigned int loc)
@@ -195,12 +225,110 @@ static void tis_send_cmd(unsigned int loc, uint8_t *buf, unsigned int i_size,
tpm_write8(TIS_STS_(loc), STS_COMMAND_READY);
}

+/************************** CRB locality & command ****************************/
+
+static void crb_request_locality(unsigned int loc)
+{
+ const uint32_t mask = CRB_LOC_STATE_LOC_ASSIGNED |
+ CRB_LOC_STATE_REG_VALID_STS;
+
+ tpm_write32(CRB_LOC_CTRL_(loc), CRB_LOC_CTRL_REQUEST_ACCESS);
+ while ( (tpm_read32(CRB_LOC_STATE_(loc)) & mask) != mask )
+ ;
+}
+
+static void crb_relinquish_locality(unsigned int loc)
+{
+ tpm_write32(CRB_LOC_CTRL_(loc), CRB_LOC_CTRL_RELINQUISH);
+ while ( tpm_read32(CRB_LOC_STATE_(loc)) & CRB_LOC_STATE_LOC_ASSIGNED )
+ ;
+}
+
+static void crb_cmd_ready(unsigned int loc)
+{
+ tpm_write32(CRB_CTRL_REQ_(loc), CRB_CTRL_REQ_CMD_READY);
+ while ( tpm_read32(CRB_CTRL_REQ_(loc)) & CRB_CTRL_REQ_CMD_READY )
+ ;
+}
+
+static void crb_go_idle(unsigned int loc)
+{
+ tpm_write32(CRB_CTRL_REQ_(loc), CRB_CTRL_REQ_GO_IDLE);
+ while ( tpm_read32(CRB_CTRL_REQ_(loc)) & CRB_CTRL_REQ_GO_IDLE )
+ ;
+}
+
+static void crb_send_cmd(unsigned int loc, uint8_t *buf, unsigned int i_size,

+ unsigned int *o_size)
+{

+ paddr_t data_buf_pa = TPM_MMIO_BASE + CRB_DATA_BUFFER_(loc);
+ unsigned int expected;
+
+ if ( i_size > CRB_DATA_BUFFER_SIZE || *o_size < sizeof(struct tpm_rsp_hdr) )
+ {
+ *o_size = 0;
+ return;
+ }
+
+ /* Out of caution, make sure no previous command is still executing. */
+ while ( tpm_read32(CRB_CTRL_START_(loc)) & CRB_CTRL_START_INVOKE )
+ ;
+
+ crb_cmd_ready(loc);
+
+ /* In an unlikely event that TPM signals irrecoverable error here,
+ * better bail out than hang in infinite loop waiting for the
+ * start condition later. */
+ if ( tpm_read32(CRB_CTRL_STS_(loc)) & CRB_CTRL_STS_ERROR )
+ {
+ *o_size = 0;
+ crb_go_idle(loc);
+ return;
+ }
+
+ tpm_write32(CRB_CTRL_CANCEL_(loc), 0);
+
+ tpm_write32(CRB_CTRL_CMD_LADDR_(loc), data_buf_pa);
+ tpm_write32(CRB_CTRL_CMD_HADDR_(loc), 0);
+ tpm_write32(CRB_CTRL_CMD_SIZE_(loc), CRB_DATA_BUFFER_SIZE);
+ tpm_write32(CRB_CTRL_RSP_SIZE_(loc), CRB_DATA_BUFFER_SIZE);
+ /* RSP_ADDR is 64-bit. */
+ tpm_write32(CRB_CTRL_RSP_ADDR_(loc), data_buf_pa);
+ tpm_write32(CRB_CTRL_RSP_ADDR_(loc) + 4, 0);
+
+ memcpy(__va(data_buf_pa), buf, i_size);
+
+ tpm_write32(CRB_CTRL_START_(loc), CRB_CTRL_START_INVOKE);
+ while ( tpm_read32(CRB_CTRL_START_(loc)) & CRB_CTRL_START_INVOKE )
+ ;
+
+ if ( tpm_read32(CRB_CTRL_STS_(loc)) & CRB_CTRL_STS_ERROR )
+ {
+ *o_size = 0;
+ crb_go_idle(loc);
+ return;
+ }
+
+ /* Read header to learn the response length. */
+ memcpy(buf, __va(data_buf_pa), sizeof(struct tpm_rsp_hdr));
+ expected = be32_to_cpu(((struct tpm_rsp_hdr *)buf)->paramSize);
+ if ( expected > *o_size )
+ expected = *o_size;
+ if ( expected > CRB_DATA_BUFFER_SIZE )
+ expected = CRB_DATA_BUFFER_SIZE;
+
+ memcpy(buf, __va(data_buf_pa), expected);
+
+ *o_size = expected;
+ crb_go_idle(loc);
+}
+
/************************** Interface dispatch ********************************/

static void request_locality(unsigned int loc)
{

if ( tpm_is_crb() )
- return;
+ crb_request_locality(loc);
else
tis_request_locality(loc);
}
@@ -208,7 +336,7 @@ static void request_locality(unsigned int loc)

static void relinquish_locality(unsigned int loc)
{

if ( tpm_is_crb() )
- return;
+ crb_relinquish_locality(loc);
else
tis_relinquish_locality(loc);
}
@@ -217,7 +345,7 @@ static void send_cmd(unsigned int loc, uint8_t *buf, unsigned int i_size,
unsigned int *o_size)
{
if ( tpm_is_crb() )
- *o_size = 0;
+ crb_send_cmd(loc, buf, i_size, o_size);
else
tis_send_cmd(loc, buf, i_size, o_size);
}
--
2.55.0

[Sergii Dmytruk]

From: Krystian Hebel <krystia...@3mdeb.com>

The file contains base address of TXT register spaces, offsets of
registers within them, error codes and inline functions for accessing
structures stored on TXT heap.

xen/arch/x86/tboot.c is updated to use definitions from this new header
instead of duplicating them. The change in tboot_protect_mem_regions()
there is caused by going from NR_TXT_CONFIG_PAGES to
TXT_CONFIG_SPACE_SIZE which avoids multiplying number of pages by page
size on every use.

Signed-off-by: Krystian Hebel <krystia...@3mdeb.com>

Signed-off-by: Sergii Dmytruk <sergii....@3mdeb.com>
---

Notes:

v4: removed unused SLAUNCH_ERROR_* #defines
v4: __ASSEMBLY__ => __ASSEMBLER__
v4: added back halt() loop before unreachable() in txt_reset() as reset is apparently asynchronous
v4: replaced txt_*_{start,size}() with an enumeration and txt_{start,size}() that iterate over entries
v4: NR_TXT_CONFIG_SIZE => TXT_CONFIG_SPACE_SIZE in one place (this was renamed but one use remained unchanged)

xen/arch/x86/include/asm/intel-txt.h | 250 +++++++++++++++++++++++++++
xen/arch/x86/tboot.c | 20 +--
2 files changed, 252 insertions(+), 18 deletions(-)
create mode 100644 xen/arch/x86/include/asm/intel-txt.h

diff --git a/xen/arch/x86/include/asm/intel-txt.h b/xen/arch/x86/include/asm/intel-txt.h
new file mode 100644
index 0000000000..15d474f002
--- /dev/null
+++ b/xen/arch/x86/include/asm/intel-txt.h
@@ -0,0 +1,250 @@

+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*

+ * Intel TXT is an implementation of DRTM in CPUs made by Intel (although CPU
+ * alone isn't enough, chipset must support TXT as well).
+ *
+ * Overview:
+ * https://www.intel.com/content/www/us/en/support/articles/000025873/processors.html
+ * Software Development Guide (SDG):
+ * https://www.intel.com/content/www/us/en/content-details/315168/
+ */
+
+#ifndef X86_INTEL_TXT_H
+#define X86_INTEL_TXT_H
+
+/*
+ * TXT configuration registers (offsets from TXT_{PUB, PRIV}_CONFIG_REGS_BASE)
+ */
+#define TXT_PUB_CONFIG_REGS_BASE 0xfed30000U
+#define TXT_PRIV_CONFIG_REGS_BASE 0xfed20000U
+
+/*
+ * The same set of registers is exposed twice (with different permissions) and
+ * they are allocated continuously with page alignment.
+ */
+#define TXT_CONFIG_SPACE_SIZE \
+ (TXT_PUB_CONFIG_REGS_BASE - TXT_PRIV_CONFIG_REGS_BASE)
+
+/* Offsets from pub/priv config space. */
+#define TXTCR_STS 0x0000
+#define TXTCR_ESTS 0x0008
+#define TXTCR_ERRORCODE 0x0030
+#define TXTCR_CMD_RESET 0x0038
+#define TXTCR_CMD_CLOSE_PRIVATE 0x0048
+#define TXTCR_DIDVID 0x0110
+#define TXTCR_VER_EMIF 0x0200
+#define TXTCR_CMD_UNLOCK_MEM_CONFIG 0x0218
+#define TXTCR_SINIT_BASE 0x0270
+#define TXTCR_SINIT_SIZE 0x0278
+#define TXTCR_MLE_JOIN 0x0290
+#define TXTCR_HEAP_BASE 0x0300
+#define TXTCR_HEAP_SIZE 0x0308
+#define TXTCR_SCRATCHPAD 0x0378
+#define TXTCR_CMD_OPEN_LOCALITY1 0x0380
+#define TXTCR_CMD_CLOSE_LOCALITY1 0x0388
+#define TXTCR_CMD_OPEN_LOCALITY2 0x0390
+#define TXTCR_CMD_CLOSE_LOCALITY2 0x0398
+#define TXTCR_CMD_SECRETS 0x08e0
+#define TXTCR_CMD_NO_SECRETS 0x08e8
+#define TXTCR_E2STS 0x08f0
+
+/*
+ * Secure Launch Defined Error Codes used in MLE-initiated TXT resets.
+ *
+ * TXT Specification
+ * Appendix I ACM Error Codes
+ */
+#define SLAUNCH_ERROR_INTEGER_OVERFLOW 0xc0008001U
+#define SLAUNCH_ERROR_HI_PMR_BASE 0xc0008002U
+#define SLAUNCH_ERROR_LO_PMR_BASE 0xc0008003U
+#define SLAUNCH_ERROR_LO_PMR_SIZE 0xc0008004U
+#define SLAUNCH_ERROR_LO_PMR_MLE 0xc0008005U
+#define SLAUNCH_ERROR_BUFFER_BEYOND_PMR 0xc0008006U
+#define SLAUNCH_ERROR_HEAP_BAD_OS2MLE 0xc0008007U
+#define SLAUNCH_ERROR_HEAP_BAD_OS2SINIT 0xc0008008U
+
+#ifndef __ASSEMBLER__
+
+/* Need to differentiate between pre- and post paging enabled. */
+#ifdef __EARLY_SLAUNCH__
+#include <xen/macros.h>
+#define _txt(x) _p(x)
+#else
+#include <xen/types.h>
+#include <asm/page.h> /* __va() */
+#define _txt(x) __va(x)
+#endif
+
+/*
+ * Always use private space as some of registers are either read-only or not
+ * present in public space.
+ */
+static inline uint64_t txt_read(unsigned int reg_no)
+{
+ volatile uint64_t *reg = _txt(TXT_PRIV_CONFIG_REGS_BASE + reg_no);
+ return *reg;
+}
+
+static inline void txt_write(unsigned int reg_no, uint64_t val)
+{
+ volatile uint64_t *reg = _txt(TXT_PRIV_CONFIG_REGS_BASE + reg_no);
+ *reg = val;
+}
+
+static inline void noreturn txt_reset(uint32_t error)
+{
+ txt_write(TXTCR_ERRORCODE, error);
+ txt_write(TXTCR_CMD_NO_SECRETS, 1);
+ txt_write(TXTCR_CMD_UNLOCK_MEM_CONFIG, 1);
+ /*
+ * Ignoring the result as this serves as a TXT register barrier after
+ * writing to TXTCR_CMD_UNLOCK_MEM_CONFIG. Must be done to ensure that any
+ * future chipset operations see the write.
+ */
+ txt_read(TXTCR_ESTS);
+ txt_write(TXTCR_CMD_RESET, 1);
+
+ while (true)
+ {
+ /*
+ * This is halt() from <asm/system.h>. Can't include the file as it
+ * breaks early code compilation.
+ */
+ asm volatile ( "hlt" : : : "memory" );
+ }
+ unreachable();
+}
+
+/*
+ * Secure Launch defined OS/MLE TXT Heap table
+ */
+struct txt_os_mle_data {
+ uint32_t version;
+ uint32_t reserved;
+ uint64_t slrt;
+ uint64_t txt_info;
+ uint32_t ap_wake_block;
+ uint32_t ap_wake_block_size;
+ uint8_t mle_scratch[64];
+} __packed;
+
+/*
+ * TXT specification defined BIOS data TXT Heap table
+ */
+struct txt_bios_data {
+ uint32_t version; /* Currently 5 for TPM 1.2 and 6 for TPM 2.0 */
+ uint32_t bios_sinit_size;
+ uint64_t reserved1;
+ uint64_t reserved2;
+ uint32_t num_logical_procs;
+ /* Versions >= 3 && < 5 */
+ uint32_t sinit_flags;
+ /* Versions >= 5 with updates in version 6 */
+ uint32_t mle_flags;
+ /* Versions >= 4 */
+ /* Ext Data Elements */
+} __packed;
+
+/*
+ * TXT specification defined OS/SINIT TXT Heap table
+ */
+struct txt_os_sinit_data {
+ uint32_t version; /* Currently 6 for TPM 1.2 and 7 for TPM 2.0 */
+ uint32_t flags; /* Reserved in version 6 */
+ uint64_t mle_ptab;
+ uint64_t mle_size;
+ uint64_t mle_hdr_base;
+ uint64_t vtd_pmr_lo_base;
+ uint64_t vtd_pmr_lo_size;
+ uint64_t vtd_pmr_hi_base;
+ uint64_t vtd_pmr_hi_size;
+ uint64_t lcp_po_base;
+ uint64_t lcp_po_size;
+ uint32_t capabilities;
+ /* Version = 5 */
+ uint64_t efi_rsdt_ptr; /* RSD*P* in versions >= 6 */
+ /* Versions >= 6 */
+ /* Ext Data Elements */
+} __packed;
+
+/*
+ * TXT specification defined SINIT/MLE TXT Heap table
+ */
+struct txt_sinit_mle_data {
+ uint32_t version; /* Current values are 6 through 9 */
+ /* Versions <= 8, fields until lcp_policy_control must be 0 for >= 9 */
+ uint8_t bios_acm_id[20];
+ uint32_t edx_senter_flags;
+ uint64_t mseg_valid;
+ uint8_t sinit_hash[20];
+ uint8_t mle_hash[20];
+ uint8_t stm_hash[20];
+ uint8_t lcp_policy_hash[20];
+ uint32_t lcp_policy_control;
+ /* Versions >= 7 */
+ uint32_t rlp_wakeup_addr;
+ uint32_t reserved;
+ uint32_t num_of_sinit_mdrs;
+ uint32_t sinit_mdrs_table_offset;
+ uint32_t sinit_vtd_dmar_table_size;
+ uint32_t sinit_vtd_dmar_table_offset;
+ /* Versions >= 8 */
+ uint32_t processor_scrtm_status;
+ /* Versions >= 9 */
+ /* Ext Data Elements */
+} __packed;
+
+/*
+ * Functions to extract data from the Intel TXT Heap Memory.
+ *
+ * The layout of the heap is dictated by TXT. It's a set of variable-sized
+ * tables that appear in pre-defined order:
+ *
+ * +------------------------------------+
+ * | Size of Bios Data table (uint64_t) |
+ * +------------------------------------+
+ * | Bios Data table |
+ * +------------------------------------+
+ * | Size of OS MLE table (uint64_t) |
+ * +------------------------------------+
+ * | OS MLE table |
+ * +-------------------------------- +
+ * | Size of OS SINIT table (uint64_t) |
+ * +------------------------------------+
+ * | OS SINIT table |
+ * +------------------------------------+
+ * | Size of SINIT MLE table (uint64_t) |
+ * +------------------------------------+
+ * | SINIT MLE table |
+ * +------------------------------------+
+ *
+ * NOTE: the table size fields include the 8 byte size field itself.
+ *
+ * NOTE: despite SDG mentioning 8-byte alignment, at least some BIOS ACM modules
+ * were observed to violate this requirement for Bios Data table, so not
+ * enforcing any alignment.
+ */
+enum {
+ TXT_BIOS,
+ TXT_OS2MLE,
+ TXT_OS2SINIT,
+ TXT_SINIT2MLE,
+};
+static inline uint64_t txt_size(const void *heap, int table_index)
+{
+ int i;
+ for (i = 0; i < table_index; ++i)
+ heap += *(const uint64_t *)heap;
+ return *(const uint64_t *)heap - sizeof(uint64_t);
+}
+static inline void *txt_start(void *heap, int table_index)
+{
+ int i;
+ for (i = 0; i < table_index; ++i)
+ heap += *(const uint64_t *)heap;
+ return heap + sizeof(uint64_t);
+}
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* X86_INTEL_TXT_H */
diff --git a/xen/arch/x86/tboot.c b/xen/arch/x86/tboot.c
index 5ae27f481f..e914177689 100644
--- a/xen/arch/x86/tboot.c
+++ b/xen/arch/x86/tboot.c
@@ -17,6 +17,7 @@
#include <asm/setup.h>
#include <asm/tboot.h>
#include <asm/trampoline.h>
+#include <asm/intel-txt.h>

#include <crypto/vmac.h>

@@ -37,23 +38,6 @@ static uint64_t __initdata sinit_base, __initdata sinit_size;

static bool __ro_after_init is_vtd;

-/*
- * TXT configuration registers (offsets from TXT_{PUB, PRIV}_CONFIG_REGS_BASE)
- */
-
-#define TXT_PUB_CONFIG_REGS_BASE 0xfed30000U
-#define TXT_PRIV_CONFIG_REGS_BASE 0xfed20000U
-
-/* # pages for each config regs space - used by fixmap */
-#define NR_TXT_CONFIG_PAGES ((TXT_PUB_CONFIG_REGS_BASE - \
- TXT_PRIV_CONFIG_REGS_BASE) >> PAGE_SHIFT)
-
-/* offsets from pub/priv config space */
-#define TXTCR_SINIT_BASE 0x0270
-#define TXTCR_SINIT_SIZE 0x0278
-#define TXTCR_HEAP_BASE 0x0300
-#define TXTCR_HEAP_SIZE 0x0308
-
#define SHA1_SIZE 20
typedef uint8_t sha1_hash_t[SHA1_SIZE];

@@ -411,7 +395,7 @@ int __init tboot_protect_mem_regions(void)

/* TXT Private Space */
rc = e820_change_range_type(&e820, TXT_PRIV_CONFIG_REGS_BASE,
- TXT_PRIV_CONFIG_REGS_BASE + NR_TXT_CONFIG_PAGES * PAGE_SIZE,
+ TXT_PRIV_CONFIG_REGS_BASE + TXT_CONFIG_SPACE_SIZE,
E820_RESERVED, E820_UNUSABLE);
if ( !rc )
return 0;
--
2.55.0

[Sergii Dmytruk]

From: Kacper Stojek <kacper...@3mdeb.com>

Measured Launched Environment (MLE) is Intel TXT specific term for DLME
(Dynamic Launch Measured Environment) which is whatever gets control
after DRTM (Dynamic Root of Trust for Measurement) is initiated.

DRTM is a way to establish hardware root of trust which excludes
firmware and is not directly tied to hardware's boot process (in
contrast to static RTM, or SRTM). A bootloader compatible with Secure
Launch specification [1] parses MLE header to know how to invoke Xen as
MLE/DLME. The header is also processed by SINIT ACM.

The new entry point is called `slaunch_stub_entry` and is used mainly to
differentiate from other kinds of boots. It moves a magic number to
`EAX` before jumping into common startup code.

[1]: https://trenchboot.org/specifications/Secure_Launch/

Signed-off-by: Kacper Stojek <kacper...@3mdeb.com>

Signed-off-by: Krystian Hebel <krystia...@3mdeb.com>
Signed-off-by: Sergii Dmytruk <sergii....@3mdeb.com>
---

Notes:

v4: was "x86/boot: add MLE header and Secure Launch entry point"
v4: added CONFIG_SLAUNCH Kconfig option
v4: expanded commit message significantly
v4: expanded the paragraph added to the documentation
v4: SLAUNCH_BOOTLOADER_MAGIC now lives here
v4: MLE header size is now computed from labels
v4: provided more details in the comment on slaunch_stub_entry
v4: handle Slaunch bootloader by just hanging (wasn't handled here in v3)
v4: use __base_reloc_end as an end of image instead of _end

docs/hypervisor-guide/x86/how-xen-boots.rst | 10 +++
xen/arch/x86/Kconfig | 8 +++
xen/arch/x86/boot/head.S | 76 +++++++++++++++++++++
3 files changed, 94 insertions(+)

diff --git a/docs/hypervisor-guide/x86/how-xen-boots.rst b/docs/hypervisor-guide/x86/how-xen-boots.rst
index 8b3229005c..a841d1e9f8 100644
--- a/docs/hypervisor-guide/x86/how-xen-boots.rst
+++ b/docs/hypervisor-guide/x86/how-xen-boots.rst
@@ -55,6 +55,16 @@ If ``CONFIG_PVH_GUEST`` was selected at build time, an Elf note is included
which indicates the ability to use the PVH boot protocol, and registers
``__pvh_start`` as the entrypoint, entered in 32bit mode.

+A combination of Multiboot 2 and Measured Launched Environment (MLE) headers
+is used to support Dynamic Root of Trust for Measurement (DRTM) for legacy
+(BIOS) boot. DRTM is a way to establish hardware root of trust which
+excludes firmware and is not directly tied to hardware's boot process. The
+separate entry point called ``slaunch_stub_entry`` is used mainly to
+differentiate from other kinds of boots. It moves a magic number to ``EAX``
+before jumping into common startup code. More details about Secure Launch
+data structures processed by Xen in this boot mode can be found in
+`<https://trenchboot.org/specifications/Secure_Launch/>`_.
+

xen.gz
~~~~~~
diff --git a/xen/arch/x86/Kconfig b/xen/arch/x86/Kconfig
index 3ce0774b8d..d8dac2dcfa 100644
--- a/xen/arch/x86/Kconfig
+++ b/xen/arch/x86/Kconfig
@@ -187,6 +187,14 @@ config TBOOT

If unsure, stay with the default.

+config SLAUNCH
+ bool "DRTM via Secure Launch support"
+ depends on INTEL
+ default y
+ help
+ Allows support for Secure Launch DRTM boot. This is a boot in a
+ measured environment which requires a compatible bootloader.
+
config X86_PSR
bool "Platform Shared Resource support" if EXPERT
default INTEL
diff --git a/xen/arch/x86/boot/head.S b/xen/arch/x86/boot/head.S
index 68b963ce6f..cbf91b23c9 100644
--- a/xen/arch/x86/boot/head.S
+++ b/xen/arch/x86/boot/head.S
@@ -4,6 +4,7 @@
#include <public/xen.h>
#include <asm/asm_defns.h>
#include <asm/fixmap.h>
+#include <asm/intel-txt.h>
#include <asm/page.h>
#include <asm/processor.h>
#include <asm/msr-index.h>
@@ -36,6 +37,7 @@
#define MB2_TT(name) (MULTIBOOT2_TAG_TYPE_##name)

#define XEN_HVM_START_MAGIC_VALUE 0x336ec578
+#define SLAUNCH_BOOTLOADER_MAGIC 0x4c534254

.macro mb2ht_args arg:req, args:vararg
.long \arg
@@ -126,6 +128,25 @@ multiboot2_header:
.size multiboot2_header, . - multiboot2_header
.type multiboot2_header, @object

+#if CONFIG_SLAUNCH
+SYM(mle_header, DATA, LOCAL, 16)
+ .long 0x9082ac5a /* UUID0 */
+ .long 0x74a7476f /* UUID1 */
+ .long 0xa2555c0f /* UUID2 */
+ .long 0x42b651cb /* UUID3 */
+ .long (.Lmle_header_end - mle_header) /* MLE header size */
+ .long 0x00020002 /* MLE version 2.2 */
+ .long (slaunch_stub_entry - start) /* Linear entry point of MLE (SINIT virt. address) */
+ .long 0x00000000 /* First valid page of MLE */
+ .long 0x00000000 /* Offset within binary of first byte of MLE */
+ .long (__base_relocs_end - start) /* Offset within binary of last byte + 1 of MLE */
+ .long 0x00000723 /* Bit vector of MLE-supported capabilities */
+ .long 0x00000000 /* Starting linear address of command line (unused) */
+ .long 0x00000000 /* Ending linear address of command line (unused) */
+.Lmle_header_end:
+ END(mle_header)
+#endif
+
.section .init.rodata, "a", @progbits

.Lbad_cpu_msg: .asciz "ERR: Not a 64-bit CPU!"
@@ -334,6 +355,43 @@ cs32_switch:
/* Jump to earlier loaded address. */
jmp *%edi

+#if CONFIG_SLAUNCH
+ /*
+ * Entry point for TrenchBoot Secure Launch on Intel TXT platforms.
+ *
+ * CPU is in 32b protected mode with paging disabled. On entry:
+ * - %ebx = %eip = MLE entry point,
+ * - stack pointer is undefined,
+ * - CS is flat 4GB code segment,
+ * - DS, ES, SS, FS and GS are undefined according to TXT SDG, but this
+ * would make it impossible to initialize GDTR, because GDT base must
+ * be relocated in the descriptor, which requires write access that
+ * CS doesn't provide. Instead we have to assume that some data
+ * segment register is set by SINIT ACM as flat 4GB data segment and
+ * choose DS as that register (LGDT instruction uses it by default).
+ *
+ * Additional restrictions:
+ * - some MSRs are partially cleared, among them IA32_MISC_ENABLE, so
+ * some capabilities might be reported as disabled even if they are
+ * supported by CPU
+ * - interrupts (including NMIs and SMIs) are disabled and must be
+ * enabled later
+ * - trying to enter real mode results in reset
+ * - APs are in a special SENTER sleep state and must be woken up by
+ * writing a non-zero value at a MONITORed address or via
+ * GETSEC[WAKEUP] instruction, depending on which is supported by a
+ * given SINIT ACM
+ */
+slaunch_stub_entry:
+ /* Calculate the load base address. */
+ mov %ebx, %esi
+ sub $sym_offs(slaunch_stub_entry), %esi
+
+ /* Mark Secure Launch boot protocol and jump to common entry. */
+ mov $SLAUNCH_BOOTLOADER_MAGIC, %eax
+ jmp .Lset_stack
+#endif /* CONFIG_SLAUNCH */
+
#ifdef CONFIG_PVH_GUEST
ELFNOTE(Xen, XEN_ELFNOTE_PHYS32_ENTRY, .long sym_offs(__pvh_start))

@@ -373,6 +431,7 @@ __start:
/* Restore the clobbered field. */
mov %edx, (%ebx)

+.Lset_stack:
/* Set up stack. */
lea STACK_SIZE - CPUINFO_sizeof + sym_esi(cpu0_stack), %esp

@@ -421,6 +480,12 @@ __start:
/* Bootloaders may set multiboot{1,2}.mem_lower to a nonzero value. */
xor %edx,%edx

+#if CONFIG_SLAUNCH
+ /* Check for TrenchBoot slaunch bootloader. */
+ cmp $SLAUNCH_BOOTLOADER_MAGIC, %eax
+ je .Lslaunch_proto
+#endif
+
/* Check for Multiboot2 bootloader. */
cmp $MULTIBOOT2_BOOTLOADER_MAGIC,%eax
je .Lmultiboot2_proto
@@ -436,6 +501,17 @@ __start:
cmovnz MB_mem_lower(%ebx),%edx
jmp trampoline_bios_setup

+#if CONFIG_SLAUNCH
+.Lslaunch_proto:
+ /*
+ * Upon reaching here, CPU state mostly matches the one set up by the
+ * bootloader with ESP, ESI and EDX being clobbered above.
+ */
+
+ /* Hang as this boot path is yet to be implemented. */
+ jmp .Lslaunch_proto
+#endif
+
.Lmultiboot2_proto:
/* Skip Multiboot2 information fixed part. */
lea (MB2_fixed_sizeof+MULTIBOOT2_TAG_ALIGN-1)(%ebx),%ecx
--
2.55.0

[Sergii Dmytruk]

The file provides constants, structures and several helper functions for
parsing SLRT.

The data described by the structures is passed to Xen by a bootloader
which initiated DRTM.

Signed-off-by: Daniel P. Smith <dps...@apertussolutions.com>
Signed-off-by: Ross Philipson <ross.ph...@oracle.com>

Signed-off-by: Sergii Dmytruk <sergii....@3mdeb.com>
---

Notes:

v4: don't define UEFI_SLR_TABLE_GUID here, it's specific to UEFI support
v4: made pointer parameter of dl_handler_func() constant

xen/include/xen/slr-table.h | 272 ++++++++++++++++++++++++++++++++++++
1 file changed, 272 insertions(+)
create mode 100644 xen/include/xen/slr-table.h

diff --git a/xen/include/xen/slr-table.h b/xen/include/xen/slr-table.h
new file mode 100644
index 0000000000..e3e5eb75f2
--- /dev/null
+++ b/xen/include/xen/slr-table.h
@@ -0,0 +1,272 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Secure Launch Resource Table definitions. This table is passed to Xen by
+ * a bootloader and contains information about pre-DRTM state necessary to
+ * restore hardware configuration, where to find TPM event log, how to call
+ * back into the bootloader (for EFI case) and what needs to be measured by
+ * Xen. In other words, this is similar to MBI in Multiboot Specification.
+ *
+ * Specification:
+ * https://trenchboot.org/specifications/Secure_Launch/
+ *
+ * Copyright (c) 2025 Apertus Solutions, LLC
+ * Copyright (c) 2025 Oracle and/or its affiliates.
+ * Copyright (c) 2026 3mdeb Sp. z o.o
+ */
+
+#ifndef XEN_SLR_TABLE_H
+#define XEN_SLR_TABLE_H
+
+#include <xen/types.h>
+
+/* SLR table header values */
+#define SLR_TABLE_MAGIC 0x4452544d
+#define SLR_TABLE_REVISION 1
+
+/* Current revisions for the policy and UEFI config */
+#define SLR_POLICY_REVISION 1
+#define SLR_UEFI_CONFIG_REVISION 1
+
+/* SLR defined architectures */
+#define SLR_INTEL_TXT 1
+#define SLR_AMD_SKINIT 2
+
+/* SLR defined bootloaders */
+#define SLR_BOOTLOADER_INVALID 0
+#define SLR_BOOTLOADER_GRUB 1
+
+/* Log formats */
+#define SLR_DRTM_TPM12_LOG 1
+#define SLR_DRTM_TPM20_LOG 2
+
+/* DRTM Policy Entry Flags */
+#define SLR_POLICY_FLAG_MEASURED 0x1
+#define SLR_POLICY_IMPLICIT_SIZE 0x2
+
+/* Array Lengths */
+#define TPM_EVENT_INFO_LENGTH 32
+#define TXT_VARIABLE_MTRRS_LENGTH 32
+
+/* Tags */
+#define SLR_ENTRY_INVALID 0x0000
+#define SLR_ENTRY_DL_INFO 0x0001
+#define SLR_ENTRY_LOG_INFO 0x0002
+#define SLR_ENTRY_DRTM_POLICY 0x0003
+#define SLR_ENTRY_INTEL_INFO 0x0004
+#define SLR_ENTRY_AMD_INFO 0x0005
+#define SLR_ENTRY_ARM_INFO 0x0006
+#define SLR_ENTRY_UEFI_INFO 0x0007
+#define SLR_ENTRY_UEFI_CONFIG 0x0008
+#define SLR_ENTRY_END 0xffff
+
+/* Entity Types */
+#define SLR_ET_UNSPECIFIED 0x0000
+#define SLR_ET_SLRT 0x0001
+#define SLR_ET_BOOT_PARAMS 0x0002
+#define SLR_ET_SETUP_DATA 0x0003
+#define SLR_ET_CMDLINE 0x0004
+#define SLR_ET_UEFI_MEMMAP 0x0005
+#define SLR_ET_RAMDISK 0x0006
+#define SLR_ET_MULTIBOOT2_INFO 0x0007
+#define SLR_ET_MULTIBOOT2_MODULE 0x0008
+#define SLR_ET_TXT_OS2MLE 0x0010
+#define SLR_ET_UNUSED 0xffff
+
+/*
+ * Primary SLR Table Header
+ */
+struct slr_table
+{
+ uint32_t magic;
+ uint16_t revision;
+ uint16_t architecture;
+ uint32_t size;
+ uint32_t max_size;
+ /* entries[] */
+} __packed;
+
+/*
+ * Common SLRT Table Header
+ */
+struct slr_entry_hdr
+{
+ uint32_t tag;
+ uint32_t size;
+} __packed;
+
+/*
+ * Boot loader context
+ */
+struct slr_bl_context
+{
+ uint16_t bootloader;
+ uint16_t reserved[3];
+ uint64_t context;
+} __packed;
+
+/*
+ * Prototype of a function pointed to by slr_entry_dl_info::dl_handler.
+ */
+typedef void (*dl_handler_func)(const struct slr_bl_context *bl_context);
+
+/*
+ * DRTM Dynamic Launch Configuration
+ */
+struct slr_entry_dl_info
+{
+ struct slr_entry_hdr hdr;
+ uint64_t dce_size;
+ uint64_t dce_base;
+ uint64_t dlme_size;
+ uint64_t dlme_base;
+ uint64_t dlme_entry;
+ struct slr_bl_context bl_context;
+ uint64_t dl_handler;
+} __packed;
+
+/*
+ * TPM Log Information
+ */
+struct slr_entry_log_info
+{
+ struct slr_entry_hdr hdr;
+ uint16_t format;
+ uint16_t reserved;
+ uint32_t size;
+ uint64_t addr;
+} __packed;
+
+/*
+ * DRTM Measurement Entry
+ */
+struct slr_policy_entry
+{
+ uint16_t pcr;
+ uint16_t entity_type;
+ uint16_t flags;
+ uint16_t reserved;
+ uint64_t size;
+ uint64_t entity;
+ char evt_info[TPM_EVENT_INFO_LENGTH];
+} __packed;
+
+/*
+ * DRTM Measurement Policy
+ */
+struct slr_entry_policy
+{
+ struct slr_entry_hdr hdr;
+ uint16_t reserved[2];
+ uint16_t revision;
+ uint16_t nr_entries;
+ struct slr_policy_entry policy_entries[];
+} __packed;
+
+/*
+ * Secure Launch defined MTRR saving structures
+ */
+struct slr_txt_mtrr_pair
+{
+ uint64_t mtrr_physbase;
+ uint64_t mtrr_physmask;
+} __packed;
+
+struct slr_txt_mtrr_state
+{
+ uint64_t default_mem_type;
+ uint64_t mtrr_vcnt;
+ struct slr_txt_mtrr_pair mtrr_pair[TXT_VARIABLE_MTRRS_LENGTH];
+} __packed;
+
+/*
+ * Intel TXT Info table
+ */
+struct slr_entry_intel_info
+{
+ struct slr_entry_hdr hdr;
+ uint64_t boot_params_base;
+ uint64_t txt_heap;
+ uint64_t saved_misc_enable_msr;
+ struct slr_txt_mtrr_state saved_bsp_mtrrs;
+} __packed;
+
+/*
+ * AMD SKINIT Info table
+ */
+struct slr_entry_amd_info
+{
+ struct slr_entry_hdr hdr;
+ uint64_t next;
+ uint32_t type;
+ uint32_t len;
+ uint64_t slrt_size;
+ uint64_t slrt_base;
+ uint64_t boot_params_base;
+ uint16_t psp_version;
+ uint16_t reserved[3];
+} __packed;
+
+/*
+ * UEFI config measurement entry
+ */
+struct slr_uefi_cfg_entry
+{
+ uint16_t pcr;
+ uint16_t reserved;
+ uint32_t size;
+ uint64_t cfg; /* address or value */
+ char evt_info[TPM_EVENT_INFO_LENGTH];
+} __packed;
+
+struct slr_entry_uefi_config
+{
+ struct slr_entry_hdr hdr;
+ uint16_t reserved[2];
+ uint16_t revision;
+ uint16_t nr_entries;
+ struct slr_uefi_cfg_entry uefi_cfg_entries[];
+} __packed;
+
+static inline const void *
+slr_end_of_entries(const struct slr_table *table)
+{
+ return (const void *)table + table->size;
+}
+
+static inline const struct slr_entry_hdr *
+slr_next_entry(const struct slr_table *table, const struct slr_entry_hdr *curr)
+{
+ const struct slr_entry_hdr *next = (void *)curr + curr->size;
+
+ if ( (void *)next + sizeof(*next) > slr_end_of_entries(table) )
+ return NULL;
+ if ( next->tag == SLR_ENTRY_END )
+ return NULL;
+ if ( (void *)next + next->size > slr_end_of_entries(table) )
+ return NULL;
+
+ return next;
+}
+
+static inline const struct slr_entry_hdr *
+slr_next_entry_by_tag(const struct slr_table *table,
+ const struct slr_entry_hdr *entry,
+ uint16_t tag)
+{
+ if ( !entry ) /* Start from the beginning */
+ entry = (void *)table + sizeof(*table);
+
+ for ( ; ; )
+ {
+ if ( entry->tag == tag )
+ return entry;
+
+ entry = slr_next_entry(table, entry);
+ if ( !entry )
+ return NULL;
+ }
+
+ return NULL;
+}
+
+#endif /* XEN_SLR_TABLE_H */
--
2.55.0

[Sergii Dmytruk]

Make head.S invoke a C function to retrieve MBI and SLRT addresses in a
platform-specific way. This is also the place to perform sanity checks
of DRTM.

Signed-off-by: Krystian Hebel <krystia...@3mdeb.com>

Signed-off-by: Sergii Dmytruk <sergii....@3mdeb.com>
---

Notes:

v4: use CONFIG_SLAUNCH
v4: expose slaunch_early_init_results via asm-offsets.c to not hard-code its size
v4: use `mov` instead of `lea` in head.S

v4: put SPDX license comment on its own line

v4: check that SLRT address is below 4 GiB
v4: perform a TXT reset with specific error codes if data doesn't meet expectations
v4: replace SLAUNCH_ERROR_GENERIC with specific error codes
v4: removed declaration and a reference to otherwise unused slaunch_get_slrt()
v4: mark `slaunch_active` variable with `__ro_after_init`
v4: updates to the handling of TXT heap sections due to different API

xen/arch/x86/Makefile | 1 +
xen/arch/x86/boot/Makefile | 12 +++++++-
xen/arch/x86/boot/head.S | 35 +++++++++++++++++++--
xen/arch/x86/boot/slaunch-early.c | 46 ++++++++++++++++++++++++++++
xen/arch/x86/include/asm/intel-txt.h | 20 ++++++++++++
xen/arch/x86/include/asm/slaunch.h | 30 ++++++++++++++++++
xen/arch/x86/slaunch.c | 32 +++++++++++++++++++
xen/arch/x86/x86_64/asm-offsets.c | 10 ++++++
8 files changed, 183 insertions(+), 3 deletions(-)
create mode 100644 xen/arch/x86/boot/slaunch-early.c
create mode 100644 xen/arch/x86/include/asm/slaunch.h
create mode 100644 xen/arch/x86/slaunch.c

diff --git a/xen/arch/x86/Makefile b/xen/arch/x86/Makefile
index 293f3bee35..a03f5a91ef 100644
--- a/xen/arch/x86/Makefile
+++ b/xen/arch/x86/Makefile
@@ -60,6 +60,7 @@ obj-$(CONFIG_COMPAT) += x86_64/physdev.o
obj-$(CONFIG_X86_PSR) += psr.o
obj-y += setup.o
obj-y += shutdown.o
+obj-$(CONFIG_SLAUNCH) += slaunch.o
obj-y += smp.o
obj-y += smpboot.o
obj-y += spec_ctrl.o
diff --git a/xen/arch/x86/boot/Makefile b/xen/arch/x86/boot/Makefile
index feae17c14a..02f690d34a 100644
--- a/xen/arch/x86/boot/Makefile
+++ b/xen/arch/x86/boot/Makefile
@@ -5,10 +5,18 @@ obj-bin-y += $(obj64)

obj32 := cmdline.32.o
obj32 += reloc.32.o
obj32 += reloc-trampoline.32.o

+ifeq ($(CONFIG_SLAUNCH),y)
+obj32 += slaunch-early.32.o
+endif

obj32 += tpm-early.32.o

obj64 := reloc-trampoline.o

+exports := cmdline_parse_early,reloc,reloc_trampoline32
+ifeq ($(CONFIG_SLAUNCH),y)
+exports := $(exports),slaunch_early_init
+endif
+
nocov-y += $(obj32) $(obj64)
noubsan-y += $(obj32) $(obj64)
targets += $(obj32)
@@ -29,6 +37,8 @@ $(obj32): XEN_CFLAGS := $(CFLAGS_x86_32) -fpic

$(obj)/%.32.o: $(src)/%.c FORCE
$(call if_changed_rule,cc_o_c)

+$(obj)/slaunch-early.32.o: XEN_CFLAGS += -D__EARLY_SLAUNCH__
+
$(obj)/tpm-early.32.o: XEN_CFLAGS += -D__EARLY_TPM__
$(obj)/tpm-early.32.o: $(src)/../tpm.c FORCE
$(call if_changed_rule,cc_o_c)
@@ -86,7 +96,7 @@ cmd_combine = \
--bin1 $(obj)/built-in-32.base.bin \
--bin2 $(obj)/built-in-32.offset.bin \
--map $(obj)/built-in-32.base.map \
- --exports cmdline_parse_early,reloc,reloc_trampoline32 \
+ --exports $(exports) \
--output $@

targets += built-in-32.S
diff --git a/xen/arch/x86/boot/head.S b/xen/arch/x86/boot/head.S
index cbf91b23c9..700d1d850e 100644
--- a/xen/arch/x86/boot/head.S
+++ b/xen/arch/x86/boot/head.S
@@ -508,8 +508,39 @@ __start:

* bootloader with ESP, ESI and EDX being clobbered above.

*/

- /* Hang as this boot path is yet to be implemented. */
- jmp .Lslaunch_proto
+ /* Save information that TrenchBoot slaunch was used. */
+ movb $1, sym_esi(slaunch_active)
+
+ /*
+ * Prepare space for output parameter of slaunch_early_init(), which is
+ * the following structure:
+ * struct slaunch_early_init_results
+ * {
+ * uint32_t mbi_pa;
+ * uint32_t slrt_pa;
+ * } __packed;
+ */
+ sub $SL_EIR_size, %esp
+
+ push %esp /* pointer to output structure */
+ mov $sym_offs(__2M_rwdata_end), %ecx /* end of target image */
+ mov $sym_offs(_start), %edx /* target base address */
+ mov %esi, %eax /* load base address */
+ /*
+ * slaunch_early_init(load/eax, tgt/edx, tgt_end/ecx, ret/stk) using
+ * fastcall calling convention.
+ */
+ call slaunch_early_init
+ add $4, %esp /* pop the fourth parameter */
+
+ /* Move outputs of slaunch_early_init() from the stack. */
+ pop %ebx /* store physical MBI address in EBX where
+ MB2 code expects it */
+ pop sym_esi(slaunch_slrt) /* save physical address of SLRT for C
+ code */
+
+ /* Move magic number expected by Multiboot 2 to EAX and fall through. */
+ movl $MULTIBOOT2_BOOTLOADER_MAGIC, %eax
#endif

.Lmultiboot2_proto:
diff --git a/xen/arch/x86/boot/slaunch-early.c b/xen/arch/x86/boot/slaunch-early.c
new file mode 100644
index 0000000000..35992cb9b3
--- /dev/null
+++ b/xen/arch/x86/boot/slaunch-early.c
@@ -0,0 +1,46 @@

+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*

+ * Early Slaunch initialization code responsible for determining location of
+ * MBI and SLRT and enforcing basic conditions.
+ *

+ * Copyright (c) 2022-2026 3mdeb Sp. z o.o. All rights reserved.
+ */
+

+#include <xen/kernel.h>
+#include <xen/slr-table.h>
+#include <xen/types.h>
+
+#include <asm/intel-txt.h>
+#include <asm/slaunch.h>
+
+void asmlinkage slaunch_early_init(uint32_t load_base_addr,
+ uint32_t tgt_base_addr,
+ uint32_t tgt_end_addr,
+ struct slaunch_early_init_results *result)
+{
+ void *txt_heap;
+ const struct txt_os_mle_data *os_mle;
+ const struct slr_table *slrt;
+ const struct slr_entry_hdr *entry;
+ const struct slr_entry_intel_info *intel_info;
+
+ txt_heap = txt_init();
+ os_mle = txt_start(txt_heap, TXT_OS2MLE);
+
+ if ( os_mle->slrt & ~0xffffffffULL )
+ txt_reset(SLAUNCH_ERROR_BAD_SLRT_ADDRESS);
+
+ result->slrt_pa = os_mle->slrt;
+
+ slrt = (const struct slr_table *)result->slrt_pa;
+
+ entry = slr_next_entry_by_tag(slrt, NULL, SLR_ENTRY_INTEL_INFO);
+ if ( entry == NULL )
+ txt_reset(SLAUNCH_ERROR_NO_VENDOR_INFO);
+
+ intel_info = container_of(entry, const struct slr_entry_intel_info, hdr);
+ if ( intel_info->hdr.size != sizeof(*intel_info) )
+ txt_reset(SLAUNCH_ERROR_BAD_VENDOR_INFO);
+
+ result->mbi_pa = intel_info->boot_params_base;
+}
diff --git a/xen/arch/x86/include/asm/intel-txt.h b/xen/arch/x86/include/asm/intel-txt.h
index 15d474f002..dc6c689f1a 100644
--- a/xen/arch/x86/include/asm/intel-txt.h
+++ b/xen/arch/x86/include/asm/intel-txt.h
@@ -62,6 +62,9 @@
#define SLAUNCH_ERROR_BUFFER_BEYOND_PMR 0xc0008006U
#define SLAUNCH_ERROR_HEAP_BAD_OS2MLE 0xc0008007U
#define SLAUNCH_ERROR_HEAP_BAD_OS2SINIT 0xc0008008U
+#define SLAUNCH_ERROR_NO_VENDOR_INFO 0xc0008009U
+#define SLAUNCH_ERROR_BAD_VENDOR_INFO 0xc000800AU
+#define SLAUNCH_ERROR_BAD_SLRT_ADDRESS 0xc000800BU

#ifndef __ASSEMBLER__

@@ -245,6 +248,23 @@ static inline void *txt_start(void *heap, int table_index)
return heap + sizeof(uint64_t);
}

+static inline void *txt_init(void)
+{
+ void *txt_heap;
+
+ /* Clear the TXT error register for a clean start of the day. */
+ txt_write(TXTCR_ERRORCODE, 0);
+
+ txt_heap = _p(txt_read(TXTCR_HEAP_BASE));
+
+ if ( txt_size(txt_heap, TXT_OS2MLE) < sizeof(struct txt_os_mle_data) )
+ txt_reset(SLAUNCH_ERROR_HEAP_BAD_OS2MLE);
+ if ( txt_size(txt_heap, TXT_OS2SINIT) < sizeof(struct txt_os_sinit_data) )
+ txt_reset(SLAUNCH_ERROR_HEAP_BAD_OS2SINIT);
+
+ return txt_heap;
+}
+
#endif /* !__ASSEMBLER__ */

#endif /* X86_INTEL_TXT_H */
diff --git a/xen/arch/x86/include/asm/slaunch.h b/xen/arch/x86/include/asm/slaunch.h
new file mode 100644
index 0000000000..24ba164c0a
--- /dev/null
+++ b/xen/arch/x86/include/asm/slaunch.h
@@ -0,0 +1,30 @@

+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*

+ * Declarations related to Slaunch (an implementation of a DRTM launch). This
+ * header is consumed by both normal and early boot code and has to take the
+ * two environments into account.
+ *
+ * More details about Slaunch are available at:

+ * https://trenchboot.org/specifications/Secure_Launch/
+ *

+ * Copyright (c) 2022-2026 3mdeb Sp. z o.o. All rights reserved.
+ */
+

+#ifndef X86_SLAUNCH_H
+#define X86_SLAUNCH_H
+
+#include <xen/types.h>
+
+struct slaunch_early_init_results
+{
+ uint32_t mbi_pa;
+ uint32_t slrt_pa;
+} __packed;
+
+/* Indicates an active Secure Launch boot. */
+extern bool slaunch_active;
+
+/* Holds physical address of SLRT. */
+extern uint32_t slaunch_slrt;
+
+#endif /* X86_SLAUNCH_H */
diff --git a/xen/arch/x86/slaunch.c b/xen/arch/x86/slaunch.c
new file mode 100644
index 0000000000..acf751804f
--- /dev/null
+++ b/xen/arch/x86/slaunch.c
@@ -0,0 +1,32 @@

+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*

+ * Main Slaunch code used during boot process.
+ *

+ * Copyright (c) 2022-2026 3mdeb Sp. z o.o. All rights reserved.
+ */
+

+#include <xen/compiler.h>
+#include <xen/init.h>
+#include <xen/inttypes.h>
+#include <xen/macros.h>
+#include <xen/sections.h>
+
+#include <asm/slaunch.h>
+
+/*
+ * These variables are assigned to by the code near Xen's entry point.
+ *
+ * slaunch_active is not __initdata to allow checking for an active Secure
+ * Launch boot at any point.
+ */
+bool __ro_after_init slaunch_active;
+uint32_t __initdata slaunch_slrt; /* physical address */
+
+/*
+ * Using slaunch_active in head.S assumes it's a single byte in size, so enforce
+ * this assumption.
+ */
+static void __maybe_unused compile_time_checks(void)
+{
+ BUILD_BUG_ON(sizeof(slaunch_active) != 1);
+}
diff --git a/xen/arch/x86/x86_64/asm-offsets.c b/xen/arch/x86/x86_64/asm-offsets.c
index baf266ab80..f0aaf0f4ba 100644
--- a/xen/arch/x86/x86_64/asm-offsets.c
+++ b/xen/arch/x86/x86_64/asm-offsets.c
@@ -16,6 +16,9 @@
#include <xen/multiboot.h>
#include <xen/multiboot2.h>
#include <asm/guest-msr.h>
+#ifdef CONFIG_SLAUNCH
+#include <asm/slaunch.h>
+#endif

#ifdef CONFIG_VIDEO
# include "../boot/video.h"
@@ -236,4 +239,11 @@ void __dummy__(void)
DEFINE(BVI_size, sizeof(struct boot_video_info));
BLANK();
#endif /* CONFIG_VIDEO */
+
+#ifdef CONFIG_SLAUNCH
+ OFFSET(SL_EIR_mbi_pa, struct slaunch_early_init_results, mbi_pa);
+ OFFSET(SL_EIR_slrt_pa, struct slaunch_early_init_results, slrt_pa);
+ DEFINE(SL_EIR_size, sizeof(struct slaunch_early_init_results));
+ BLANK();
+#endif
}
--
2.55.0

[Sergii Dmytruk]

From: Krystian Hebel <krystia...@3mdeb.com>

The tests validate that important parts of memory are protected against
DMA attacks, including Xen and MBI. Modules can be tested later, when it
is possible to report issues to a user before invoking TXT reset.

The protection used here is Protected Memory Regions (PMRs), which is
not available on modern hardware like MeteorLake that uses TXT DMA
Protection Ranges (TPR) and is to be added separately.

TPM event log validation is temporarily disabled due to an issue with
its allocation by bootloader (GRUB) which will need to be modified to
address this. Ultimately event log will also have to be validated early
as it is used immediately after these tests to hold MBI measurements.
See larger comment in txt_verify_pmr_ranges().

Signed-off-by: Krystian Hebel <krystia...@3mdeb.com>
Signed-off-by: Sergii Dmytruk <sergii....@3mdeb.com>
---

Notes:

v4: was "x86/boot/slaunch-early: early TXT checks and boot data retrieval"

v4: updates to the handling of TXT heap sections due to different API

v4: use `bool` instead of `int` in two places
v4: don't use low range in is_in_pmr(), it must be zero
v4: use `struct multiboot2_fixed_t` instead of casting and dereferencing `uint32_t *`
v4: TPM event log check being covered by PMR can't be safely uncommented without constraining where TPM event log is allocated

xen/arch/x86/boot/slaunch-early.c | 6 ++
xen/arch/x86/include/asm/intel-txt.h | 118 +++++++++++++++++++++++++++
2 files changed, 124 insertions(+)

diff --git a/xen/arch/x86/boot/slaunch-early.c b/xen/arch/x86/boot/slaunch-early.c
index 35992cb9b3..00c772cfdf 100644
--- a/xen/arch/x86/boot/slaunch-early.c
+++ b/xen/arch/x86/boot/slaunch-early.c
@@ -21,11 +21,14 @@ void asmlinkage slaunch_early_init(uint32_t load_base_addr,
void *txt_heap;
const struct txt_os_mle_data *os_mle;
const struct slr_table *slrt;
+ const struct txt_os_sinit_data *os_sinit;
const struct slr_entry_hdr *entry;
const struct slr_entry_intel_info *intel_info;
+ uint32_t size = tgt_end_addr - tgt_base_addr;

txt_heap = txt_init();
os_mle = txt_start(txt_heap, TXT_OS2MLE);
+ os_sinit = txt_start(txt_heap, TXT_OS2SINIT);

if ( os_mle->slrt & ~0xffffffffULL )

txt_reset(SLAUNCH_ERROR_BAD_SLRT_ADDRESS);
@@ -43,4 +46,7 @@ void asmlinkage slaunch_early_init(uint32_t load_base_addr,
txt_reset(SLAUNCH_ERROR_BAD_VENDOR_INFO);

result->mbi_pa = intel_info->boot_params_base;
+

+ txt_verify_pmr_ranges(os_mle, os_sinit, intel_info,
+ load_base_addr, tgt_base_addr, size);
}
diff --git a/xen/arch/x86/include/asm/intel-txt.h b/xen/arch/x86/include/asm/intel-txt.h
index dc6c689f1a..66039dbeee 100644
--- a/xen/arch/x86/include/asm/intel-txt.h
+++ b/xen/arch/x86/include/asm/intel-txt.h
@@ -68,6 +68,9 @@

#ifndef __ASSEMBLER__

+#include <xen/multiboot2.h>
+#include <xen/slr-table.h>
+

/* Need to differentiate between pre- and post paging enabled. */

#ifdef __EARLY_SLAUNCH__
#include <xen/macros.h>
@@ -265,6 +268,121 @@ static inline void *txt_init(void)
return txt_heap;
}

+static inline bool is_in_pmr(const struct txt_os_sinit_data *os_sinit,
+ uint64_t base, uint32_t size, bool check_high)
+{
+ /* Check for size overflow. */
+ if ( base + size < base )
+ txt_reset(SLAUNCH_ERROR_INTEGER_OVERFLOW);
+
+ /*
+ * txt_verify_pmr_ranges() makes sure the low range always starts at 0, so
+ * its size is also end address.
+ */
+ if ( base + size <= os_sinit->vtd_pmr_lo_size )
+ return true;
+
+ if ( check_high && os_sinit->vtd_pmr_hi_size != 0 )
+ {
+ if ( base >= os_sinit->vtd_pmr_hi_base &&
+ base + size <= os_sinit->vtd_pmr_hi_base +
+ os_sinit->vtd_pmr_hi_size )
+ return true;
+ }
+
+ return false;
+}
+
+static inline void txt_verify_pmr_ranges(
+ const struct txt_os_mle_data *os_mle,
+ const struct txt_os_sinit_data *os_sinit,
+ const struct slr_entry_intel_info *info,
+ uint32_t load_base_addr,
+ uint32_t tgt_base_addr,
+ uint32_t xen_size)
+{
+ bool check_high_pmr = false;
+
+ /* Verify the value of the low PMR base. It should always be 0. */
+ if ( os_sinit->vtd_pmr_lo_base != 0 )
+ txt_reset(SLAUNCH_ERROR_LO_PMR_BASE);
+
+ /*
+ * Low PMR size should not be 0 on current platforms. There is an ongoing
+ * transition to TPR-based DMA protection instead of PMR-based; this is not
+ * yet supported by the code.
+ */
+ if ( os_sinit->vtd_pmr_lo_size == 0 )
+ txt_reset(SLAUNCH_ERROR_LO_PMR_SIZE);
+
+ /* Check if regions overlap. Treat regions with no hole between as error. */
+ if ( os_sinit->vtd_pmr_hi_size != 0 &&
+ os_sinit->vtd_pmr_hi_base <= os_sinit->vtd_pmr_lo_size )
+ txt_reset(SLAUNCH_ERROR_HI_PMR_BASE);
+
+ /* Check for size overflow. */
+ if ( os_sinit->vtd_pmr_hi_base + os_sinit->vtd_pmr_hi_size <
+ os_sinit->vtd_pmr_hi_size )
+ txt_reset(SLAUNCH_ERROR_INTEGER_OVERFLOW);
+
+ /* All regions accessed by 32b code must be below 4G. */
+ if ( os_sinit->vtd_pmr_hi_base + os_sinit->vtd_pmr_hi_size <=
+ 0x100000000ULL )
+ check_high_pmr = true;
+
+ /*
+ * ACM checks that TXT heap and MLE memory is protected against DMA. We have
+ * to check if MBI and whole Xen memory is protected. The latter is done in
+ * case bootloader failed to set whole image as MLE and to make sure that
+ * both pre- and post-relocation code is protected.
+ */
+
+ /* Check if all of Xen before relocation is protected. */
+ if ( !is_in_pmr(os_sinit, load_base_addr, xen_size, check_high_pmr) )
+ txt_reset(SLAUNCH_ERROR_LO_PMR_MLE);
+
+ /* Check if all of Xen after relocation is protected. */
+ if ( load_base_addr != tgt_base_addr &&
+ !is_in_pmr(os_sinit, tgt_base_addr, xen_size, check_high_pmr) )
+ txt_reset(SLAUNCH_ERROR_LO_PMR_MLE);
+
+ /* If present, check that MBI is protected. */
+ if ( info->boot_params_base != 0 )
+ {
+ const multiboot2_fixed_t *mbi =
+ (const multiboot2_fixed_t *)(uintptr_t)info->boot_params_base;
+
+ if ( !is_in_pmr(os_sinit, info->boot_params_base, mbi->total_size,
+ check_high_pmr) )
+ txt_reset(SLAUNCH_ERROR_BUFFER_BEYOND_PMR);
+ }
+
+ /* Check if TPM event log (if present) is protected. */
+ /*
+ * FIXME: currently commented out as GRUB allocates it in a hole between
+ * PMR and reserved RAM, due to 2MB resolution of PMR. There are no other
+ * easy-to-use DMA protection mechanisms that would allow to protect that
+ * part of memory. TPR (TXT DMA Protection Range) gives 1MB resolution, but
+ * it still wouldn't be enough.
+ *
+ * One possible solution would be for GRUB to allocate log at lower address,
+ * but this would further increase memory space fragmentation. Another
+ * option is to align PMR up instead of down, making PMR cover part of
+ * reserved region, but it is unclear what the consequences may be.
+ *
+ * In tboot this issue was resolved by reserving leftover chunks of memory
+ * in e820 and/or UEFI memory map. This is also a valid solution, but would
+ * require more changes to GRUB than the ones listed above, as event log is
+ * allocated much earlier than PMRs.
+ */
+ /*
+ if ( os_mle->evtlog_addr != 0 && os_mle->evtlog_size != 0 &&
+ !is_in_pmr(os_sinit, os_mle->evtlog_addr, os_mle->evtlog_size,
+ check_high_pmr) )
+ txt_reset(SLAUNCH_ERROR_BUFFER_BEYOND_PMR);
+ */

+}
+
#endif /* !__ASSEMBLER__ */

#endif /* X86_INTEL_TXT_H */

--
2.55.0

[Sergii Dmytruk]

From: Kacper Stojek <kacper...@3mdeb.com>

TXT heap, SINIT and TXT private space are marked as reserved or unused
in e820 to protect from unintended uses.

Signed-off-by: Kacper Stojek <kacper...@3mdeb.com>
Signed-off-by: Krystian Hebel <krystia...@3mdeb.com>
Signed-off-by: Michał Żygowski <michal....@3mdeb.com>

Signed-off-by: Sergii Dmytruk <sergii....@3mdeb.com>
---

Notes:

v4: use CONFIG_SLAUNCH
v4: use unsigned long constant in PREBUILT_MAP_LIMIT #define
v4: add slaunch-tpm unit for TPM-related code specific to Slaunch (builds as normal and early code)
v4: slaunch_get_slrt() now makes its first appearance in this commit
v4: slaunch_find_log() is now defined in slaunch-tpm.c
v4: improved signature and comment for slaunch_map_l2()
v4: moved SPDX license comments to their own lines
v4: reduced txt_heap_base and txt_heap_size from 64-bit to 32-bit
v4: changed reserve_ram() to return bool and not take type (it's always the same) and skip already reserved memory
v4: switch from "(from - to)" ranges to "[from, to)" in prints
v4: verify that slaunch_map_l2() was passed a range below 4 GiB
v4: move PREBUILT_MAP_LIMIT from asm/mm.h to asm/setup.h

xen/arch/x86/Makefile | 2 +
xen/arch/x86/include/asm/intel-txt.h | 6 ++
xen/arch/x86/include/asm/setup.h | 3 +
xen/arch/x86/include/asm/slaunch-tpm.h | 19 +++++
xen/arch/x86/include/asm/slaunch.h | 34 +++++++-
xen/arch/x86/intel-txt.c | 113 +++++++++++++++++++++++++
xen/arch/x86/setup.c | 10 ++-
xen/arch/x86/slaunch-tpm.c | 36 ++++++++
xen/arch/x86/slaunch.c | 105 ++++++++++++++++++++++-
9 files changed, 323 insertions(+), 5 deletions(-)
create mode 100644 xen/arch/x86/include/asm/slaunch-tpm.h

create mode 100644 xen/arch/x86/intel-txt.c
create mode 100644 xen/arch/x86/slaunch-tpm.c

diff --git a/xen/arch/x86/Makefile b/xen/arch/x86/Makefile
index a03f5a91ef..8dbb76a3a0 100644
--- a/xen/arch/x86/Makefile
+++ b/xen/arch/x86/Makefile
@@ -42,6 +42,7 @@ obj-y += i387.o
obj-y += i8259.o
obj-$(CONFIG_INDIRECT_THUNK) += indirect-thunk.o
obj-$(CONFIG_RETURN_THUNK) += indirect-thunk.o
+obj-$(CONFIG_SLAUNCH) += intel-txt.o
obj-$(CONFIG_PV) += ioport_emulate.o
obj-y += io_apic.o
obj-y += irq.o
@@ -61,6 +62,7 @@ obj-$(CONFIG_X86_PSR) += psr.o

obj-y += setup.o
obj-y += shutdown.o

obj-$(CONFIG_SLAUNCH) += slaunch.o
+obj-$(CONFIG_SLAUNCH) += slaunch-tpm.o

obj-y += smp.o
obj-y += smpboot.o
obj-y += spec_ctrl.o

diff --git a/xen/arch/x86/include/asm/intel-txt.h b/xen/arch/x86/include/asm/intel-txt.h
index 66039dbeee..db6b0defd0 100644
--- a/xen/arch/x86/include/asm/intel-txt.h
+++ b/xen/arch/x86/include/asm/intel-txt.h
@@ -383,6 +383,12 @@ static inline void txt_verify_pmr_ranges(
*/
}

+/* Prepares for accesses to TXT-specific memory. */
+void txt_map_mem_regions(void);
+
+/* Marks TXT-specific memory as used to avoid its corruption. */
+void txt_reserve_mem_regions(void);

+
#endif /* !__ASSEMBLER__ */

#endif /* X86_INTEL_TXT_H */

diff --git a/xen/arch/x86/include/asm/setup.h b/xen/arch/x86/include/asm/setup.h
index b01e83a8ed..431c0a26b5 100644
--- a/xen/arch/x86/include/asm/setup.h
+++ b/xen/arch/x86/include/asm/setup.h
@@ -4,6 +4,9 @@
#include <xen/multiboot.h>
#include <asm/numa.h>

+/* How much of the directmap is prebuilt at compile time. */
+#define PREBUILT_MAP_LIMIT (1UL << L2_PAGETABLE_SHIFT)
+
extern const char __2M_text_start[], __2M_text_end[];
extern const char __2M_rodata_start[], __2M_rodata_end[];
extern char __2M_init_start[], __2M_init_end[];
diff --git a/xen/arch/x86/include/asm/slaunch-tpm.h b/xen/arch/x86/include/asm/slaunch-tpm.h
new file mode 100644
index 0000000000..68e9c8358a
--- /dev/null
+++ b/xen/arch/x86/include/asm/slaunch-tpm.h
@@ -0,0 +1,19 @@

+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*

+ * TPM-related functions of Slaunch. Can be used in both normal and early boot
+ * environments.
+ *
+ * Copyright (c) 2026 3mdeb Sp. z o.o. All rights reserved.
+ */
+
+#ifndef X86_SLAUNCH_TPM_H
+#define X86_SLAUNCH_TPM_H
+
+#include <xen/types.h>
+
+struct slr_table;
+
+void slaunch_find_log(const struct slr_table *slrt, paddr_t *evt_log,
+ uint32_t *evt_log_size);
+
+#endif /* X86_SLAUNCH_TPM_H */
diff --git a/xen/arch/x86/include/asm/slaunch.h b/xen/arch/x86/include/asm/slaunch.h
index 24ba164c0a..3df7174b4b 100644
--- a/xen/arch/x86/include/asm/slaunch.h
+++ b/xen/arch/x86/include/asm/slaunch.h
@@ -13,6 +13,8 @@
#ifndef X86_SLAUNCH_H
#define X86_SLAUNCH_H

+#include <xen/kernel.h>
+#include <xen/slr-table.h>
#include <xen/types.h>

struct slaunch_early_init_results
@@ -24,7 +26,37 @@ struct slaunch_early_init_results

/* Indicates an active Secure Launch boot. */

extern bool slaunch_active;

-/* Holds physical address of SLRT. */
+/*
+ * Holds physical address of SLRT. Use slaunch_get_slrt() to access SLRT
+ * instead of mapping where this points to.
+ */
extern uint32_t slaunch_slrt;

+/*
+ * Retrieves pointer to SLRT. Checks table's validity and maps it as necessary.
+ */
+struct slr_table *slaunch_get_slrt(void);
+
+/*
+ * Prepares for accesses to essential data structures setup by boot environment.
+ */
+void slaunch_map_mem_regions(void);
+
+/* Marks regions of memory as used to avoid their corruption. */
+void slaunch_reserve_mem_regions(void);
+
+/*
+ * This helper function is used to map memory below 4 GiB using L2 page tables
+ * by aligning mapped regions to 2MB. This way page allocator (which at this
+ * point isn't yet initialized) isn't needed for creating new L1 mappings. The
+ * function also checks and skips memory already mapped by the prebuilt tables.
+ *
+ * There is no unmap_l2() because the function is meant to be used by the code
+ * that accesses DRTM-related memory soon after which Xen rebuilds memory maps,
+ * effectively dropping all existing mappings.
+ *
+ * Returns zero on success.
+ */
+int slaunch_map_l2(paddr_t paddr, size_t size);
+
#endif /* X86_SLAUNCH_H */
diff --git a/xen/arch/x86/intel-txt.c b/xen/arch/x86/intel-txt.c
new file mode 100644
index 0000000000..4a42abf8df
--- /dev/null
+++ b/xen/arch/x86/intel-txt.c
@@ -0,0 +1,113 @@

+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*

+ * Functions related to DRTM on Intel using its TXT (Trusted eXecution
+ * Technology).

+ *
+ * Copyright (c) 2022-2026 3mdeb Sp. z o.o. All rights reserved.
+ */
+

+#include <xen/bug.h>
+#include <xen/init.h>
+#include <xen/lib.h>
+#include <xen/types.h>
+#include <asm/e820.h>

+#include <asm/intel-txt.h>
+#include <asm/slaunch.h>
+

+/*
+ * Corresponding TXT registers seem to have 64-bits allocated for them, yet the
+ * actual values are 32-bit long, so using the latter.
+ */
+static uint32_t __initdata txt_heap_base, txt_heap_size;
+
+void __init txt_map_mem_regions(void)
+{
+ int rc;
+
+ rc = slaunch_map_l2(TXT_PRIV_CONFIG_REGS_BASE, TXT_CONFIG_SPACE_SIZE);
+ BUG_ON(rc != 0);
+
+ txt_heap_base = txt_read(TXTCR_HEAP_BASE);
+ BUG_ON(txt_heap_base == 0);
+
+ txt_heap_size = txt_read(TXTCR_HEAP_SIZE);
+ BUG_ON(txt_heap_size == 0);
+
+ rc = slaunch_map_l2(txt_heap_base, txt_heap_size);
+ BUG_ON(rc != 0);
+}
+
+/* Mark a RAM region as reserved if it isn't marked that way already. */
+static bool __init reserve_ram(struct e820map *map, uint64_t start,
+ uint64_t end)
+{

+ unsigned int i;
+

+ for ( i = 0; i < map->nr_map; i++ )
+ {
+ uint64_t rs = map->map[i].addr;
+ uint64_t re = rs + map->map[i].size;
+
+ /* The entry includes the range. */
+ if ( start >= rs && end <= re )
+ break;
+
+ /* The entry intersects the range. */
+ if ( end > rs && start < re )
+ {
+ /* Fatal failure. */

+ return false;
+ }
+ }

+
+ /*
+ * If the range is not included by any entry and no entry intersects it,
+ * then it's not listed in the memory map. Consider this case as a success
+ * since we're only preventing RAM from being used and unlisted range should
+ * not be used.
+ */
+ if ( i == map->nr_map )
+ return true;
+
+ /*
+ * e820_change_range_type() fails if the range is already marked with the
+ * desired type. Don't consider it an error if firmware has done it for us.
+ */
+ if ( map->map[i].type == E820_RESERVED )
+ return true;
+
+ return e820_change_range_type(map, start, end, E820_RAM, E820_RESERVED);
+}
+
+void __init txt_reserve_mem_regions(void)
+{
+ bool ok;
+ uint32_t sinit_base, sinit_size;
+
+ /* TXT Heap */
+ BUG_ON(txt_heap_base == 0);
+ printk("SLAUNCH: reserving TXT heap range [%#x, %#x)\n", txt_heap_base,
+ txt_heap_base + txt_heap_size);
+ ok = reserve_ram(&e820_raw, txt_heap_base, txt_heap_base + txt_heap_size);
+ BUG_ON(!ok);
+
+ sinit_base = txt_read(TXTCR_SINIT_BASE);
+ BUG_ON(sinit_base == 0);
+
+ sinit_size = txt_read(TXTCR_SINIT_SIZE);
+ BUG_ON(sinit_size == 0);
+
+ /* SINIT */
+ printk("SLAUNCH: reserving SINIT memory range [%#x, %#x)\n", sinit_base,
+ sinit_base + sinit_size);
+ ok = reserve_ram(&e820_raw, sinit_base, sinit_base + sinit_size);
+ BUG_ON(!ok);
+
+ /* TXT Private Space */
+ printk("SLAUNCH: reserving private TXT registers range [%#x, %#x)\n",
+ TXT_PRIV_CONFIG_REGS_BASE,
+ TXT_PRIV_CONFIG_REGS_BASE + TXT_CONFIG_SPACE_SIZE);
+ ok = reserve_ram(&e820_raw, TXT_PRIV_CONFIG_REGS_BASE,
+ TXT_PRIV_CONFIG_REGS_BASE + TXT_CONFIG_SPACE_SIZE);
+ BUG_ON(!ok);
+}
diff --git a/xen/arch/x86/setup.c b/xen/arch/x86/setup.c
index 7d71fea6c0..5494fa1621 100644
--- a/xen/arch/x86/setup.c
+++ b/xen/arch/x86/setup.c
@@ -50,6 +50,7 @@
#include <asm/pv/domain.h>
#include <asm/setup.h>
#include <asm/shstk.h>
+#include <asm/slaunch.h>
#include <asm/smp.h>
#include <asm/spec_ctrl.h>
#include <asm/stubs.h>
@@ -1128,9 +1129,6 @@ static struct domain *__init create_dom0(struct boot_info *bi)
return d;
}

-/* How much of the directmap is prebuilt at compile time. */
-#define PREBUILT_MAP_LIMIT (1 << L2_PAGETABLE_SHIFT)
-
void asmlinkage __init noreturn __start_xen(void)
{
const char *memmap_type = NULL;
@@ -1472,6 +1470,12 @@ void asmlinkage __init noreturn __start_xen(void)
#endif
}

+ if ( slaunch_active )
+ {
+ slaunch_map_mem_regions();
+ slaunch_reserve_mem_regions();
+ }
+
/* Sanitise the raw E820 map to produce a final clean version. */
max_page = raw_max_page = init_e820(memmap_type, &e820_raw);

diff --git a/xen/arch/x86/slaunch-tpm.c b/xen/arch/x86/slaunch-tpm.c
new file mode 100644
index 0000000000..f59170594d
--- /dev/null
+++ b/xen/arch/x86/slaunch-tpm.c
@@ -0,0 +1,36 @@

+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*

+ * Slaunch functions related to TPM.

+ *
+ * Copyright (c) 2022-2026 3mdeb Sp. z o.o. All rights reserved.
+ */
+

+#include <xen/macros.h>

+#include <xen/slr-table.h>
+#include <xen/types.h>
+

+void slaunch_find_log(const struct slr_table *slrt, paddr_t *evt_log,
+ uint32_t *evt_log_size)
+{
+ const struct slr_entry_hdr *hdr;
+
+ hdr = slr_next_entry_by_tag(slrt, NULL, SLR_ENTRY_LOG_INFO);
+ if ( hdr != NULL )
+ {
+ const struct slr_entry_log_info *log_info;
+ log_info = container_of(hdr, const struct slr_entry_log_info, hdr);
+
+ *evt_log = (uintptr_t)_p(log_info->addr);
+ *evt_log_size = log_info->size;
+ }
+ else
+ {
+ /*
+ * Event log is used to verify measurements, but values of PCRs is the
+ * real authoritative source of information, so keep going if there is
+ * no log as secrets may still be correctly unsealed by TPM.
+ */
+ *evt_log = 0;
+ *evt_log_size = 0;
+ }
+}
diff --git a/xen/arch/x86/slaunch.c b/xen/arch/x86/slaunch.c
index acf751804f..ba1ba61c47 100644
--- a/xen/arch/x86/slaunch.c
+++ b/xen/arch/x86/slaunch.c
@@ -7,11 +7,17 @@

#include <xen/compiler.h>
#include <xen/init.h>
-#include <xen/inttypes.h>
#include <xen/macros.h>
+#include <xen/mm.h>
#include <xen/sections.h>
+#include <xen/types.h>

+#include <asm/e820.h>
+#include <asm/intel-txt.h>
+#include <asm/page.h>
+#include <asm/setup.h>
#include <asm/slaunch.h>
+#include <asm/slaunch-tpm.h>

/*

* These variables are assigned to by the code near Xen's entry point.

@@ -30,3 +36,100 @@ static void __maybe_unused compile_time_checks(void)
{
BUILD_BUG_ON(sizeof(slaunch_active) != 1);
}
+
+struct slr_table *__init slaunch_get_slrt(void)
+{
+ static struct slr_table *__initdata slrt;
+
+ if ( slrt == NULL )
+ {
+ int rc;
+
+ slrt = __va(slaunch_slrt);
+
+ rc = slaunch_map_l2(slaunch_slrt, PAGE_SIZE);
+ BUG_ON(rc != 0);
+
+ if ( slrt->magic != SLR_TABLE_MAGIC )
+ panic("SLRT has invalid magic value: %#x!\n", slrt->magic);
+ /* XXX: are newer revisions allowed? */
+ if ( slrt->revision != SLR_TABLE_REVISION )
+ panic("SLRT is of unsupported revision: %#x!\n", slrt->revision);
+ if ( slrt->architecture != SLR_INTEL_TXT )
+ panic("SLRT is for unexpected architecture: %#x!\n",
+ slrt->architecture);
+ if ( slrt->size > slrt->max_size )
+ panic("SLRT is larger than its max size: %#x > %#x!\n",
+ slrt->size, slrt->max_size);
+
+ if ( slrt->size > PAGE_SIZE )
+ {
+ rc = slaunch_map_l2(slaunch_slrt, slrt->size);
+ BUG_ON(rc != 0);
+ }
+ }
+
+ return slrt;
+}
+
+void __init slaunch_map_mem_regions(void)
+{
+ int rc;
+ paddr_t evt_log_addr;
+ uint32_t evt_log_size;
+
+ /* Vendor-specific part. */
+ txt_map_mem_regions();
+
+ slaunch_find_log(slaunch_get_slrt(), &evt_log_addr, &evt_log_size);
+ if ( evt_log_addr != 0 )
+ {
+ rc = slaunch_map_l2(evt_log_addr, evt_log_size);
+ BUG_ON(rc != 0);
+ }
+}
+
+void __init slaunch_reserve_mem_regions(void)
+{
+ paddr_t evt_log_addr;
+ uint32_t evt_log_size;
+
+ /* Vendor-specific part. */
+ txt_reserve_mem_regions();
+
+ slaunch_find_log(slaunch_get_slrt(), &evt_log_addr, &evt_log_size);
+ if ( evt_log_addr != 0 )
+ {
+ int ok;
+
+ printk("SLAUNCH: reserving event log [%#lx, %#lx)\n", evt_log_addr,
+ evt_log_addr + evt_log_size);
+ ok = reserve_e820_ram(&e820_raw, evt_log_addr,
+ evt_log_addr + evt_log_size);
+ BUG_ON(!ok);
+ }
+}
+
+int __init slaunch_map_l2(paddr_t paddr, size_t size)
+{
+ unsigned long aligned_paddr = paddr & ~((1ULL << L2_PAGETABLE_SHIFT) - 1);
+ unsigned long pages = ((paddr + size) - aligned_paddr);
+
+ pages = ROUNDUP(pages, 1ULL << L2_PAGETABLE_SHIFT) >> PAGE_SHIFT;
+
+ BUG_ON(paddr >= (1ULL << 32));
+ BUG_ON(paddr + pages * PAGE_SIZE >= (1ULL << 32));
+
+ if ( aligned_paddr + pages * PAGE_SIZE <= PREBUILT_MAP_LIMIT )
+ return 0;
+
+ if ( aligned_paddr < PREBUILT_MAP_LIMIT )
+ {
+ pages -= (PREBUILT_MAP_LIMIT - aligned_paddr) >> PAGE_SHIFT;
+ aligned_paddr = PREBUILT_MAP_LIMIT;
+ }
+
+ return map_pages_to_xen((uintptr_t)__va(aligned_paddr),
+ maddr_to_mfn(aligned_paddr),
+ pages, PAGE_HYPERVISOR);
+}
--
2.55.0

[Sergii Dmytruk]

From: Krystian Hebel <krystia...@3mdeb.com>

In preparation for TXT SENTER call, GRUB had to modify MTRR settings
to be UC for everything except SINIT ACM. Old values are restored
from SLRT where they were saved by the bootloader.

Signed-off-by: Krystian Hebel <krystia...@3mdeb.com>
Signed-off-by: Michał Żygowski <michal....@3mdeb.com>
Signed-off-by: Sergii Dmytruk <sergii....@3mdeb.com>
---

Notes:

v4: now this commit makes two functions of mtrr/generic.c public
v4: take CONFIG_SLAUNCH into account
v4: restore MTRRs earlier: move from mtrr_top_of_ram() to machine_specific_memory_setup()
v4: renamed parameter of txt_restore_mtrrs(): e820_verbose => verbose
v4: don't use rdmsrl() and wrmsrl()
v4: extract part of an integer consistently (`mtrr_cap` in txt_restore_mtrrs(), was a mix of `(uint8_t)` cast and `& 0xff`)
v4: use container_of()
v4: manage MTRR count in txt_restore_mtrrs() better (separate variable, no weird ?: operator)

xen/arch/x86/cpu/mtrr/generic.c | 9 +--
xen/arch/x86/e820.c | 5 ++
xen/arch/x86/include/asm/intel-txt.h | 3 +
xen/arch/x86/include/asm/mtrr.h | 8 +++
xen/arch/x86/include/asm/slaunch.h | 8 +++
xen/arch/x86/intel-txt.c | 84 ++++++++++++++++++++++++++++
6 files changed, 110 insertions(+), 7 deletions(-)

diff --git a/xen/arch/x86/cpu/mtrr/generic.c b/xen/arch/x86/cpu/mtrr/generic.c
index 86eb0f405b..c179935dd3 100644
--- a/xen/arch/x86/cpu/mtrr/generic.c
+++ b/xen/arch/x86/cpu/mtrr/generic.c
@@ -14,11 +14,6 @@
#include <asm/cpufeature.h>
#include "mtrr.h"

-struct mtrr_pausing_state {
- bool pge;
- uint64_t def_type;
-};
-

static const struct fixed_range_block {
uint32_t base_msr; /* start address of an MTRR block */
unsigned int ranges; /* number of MTRRs in this block */

@@ -440,7 +435,7 @@ static DEFINE_SPINLOCK(set_atomicity_lock);

* has been called.
*/

-static void mtrr_pause_caching(struct mtrr_pausing_state *state)
+void mtrr_pause_caching(struct mtrr_pausing_state *state)
{
unsigned long cr4;

@@ -481,7 +476,7 @@ static void mtrr_pause_caching(struct mtrr_pausing_state *state)

alternative("wbinvd", "", X86_FEATURE_XEN_SELFSNOOP);
}

-static void mtrr_resume_caching(struct mtrr_pausing_state state)
+void mtrr_resume_caching(struct mtrr_pausing_state state)

{
/* Intel (P6) standard MTRRs */

mtrr_wrmsr(MSR_MTRRdefType, state.def_type);
diff --git a/xen/arch/x86/e820.c b/xen/arch/x86/e820.c
index 872208ab37..c63b0b12cc 100644
--- a/xen/arch/x86/e820.c
+++ b/xen/arch/x86/e820.c
@@ -11,6 +11,8 @@
#include <asm/mtrr.h>
#include <asm/msr.h>
#include <asm/guest.h>
+#include <asm/intel-txt.h>
+#include <asm/slaunch.h>

/*
* opt_mem: Limit maximum address of physical RAM.
@@ -499,6 +501,9 @@ static void __init machine_specific_memory_setup(struct e820map *raw)
uint64_t top_of_ram, size;
unsigned int i;

+ if ( slaunch_active )

+ txt_restore_mtrrs(e820_verbose);
+
sanitize_e820_map(raw->map, &raw->nr_map);
copy_e820_map(raw->map, raw->nr_map);

diff --git a/xen/arch/x86/include/asm/intel-txt.h b/xen/arch/x86/include/asm/intel-txt.h
index db6b0defd0..406929fac2 100644
--- a/xen/arch/x86/include/asm/intel-txt.h
+++ b/xen/arch/x86/include/asm/intel-txt.h
@@ -389,6 +389,9 @@ void txt_map_mem_regions(void);

/* Marks TXT-specific memory as used to avoid its corruption. */

void txt_reserve_mem_regions(void);

+/* Restores original MTRR values saved by a bootloader before starting DRTM. */
+void txt_restore_mtrrs(bool verbose);

+
#endif /* !__ASSEMBLER__ */

#endif /* X86_INTEL_TXT_H */

diff --git a/xen/arch/x86/include/asm/mtrr.h b/xen/arch/x86/include/asm/mtrr.h
index 3a5b4f5b6e..bf82af8c47 100644
--- a/xen/arch/x86/include/asm/mtrr.h
+++ b/xen/arch/x86/include/asm/mtrr.h
@@ -63,6 +63,14 @@ extern uint8_t pat_type_2_pte_flags(uint8_t pat_type);
extern void mtrr_aps_sync_begin(void);
extern void mtrr_aps_sync_end(void);

+struct mtrr_pausing_state {
+ bool pge;
+ uint64_t def_type;
+};
+

+extern void mtrr_pause_caching(struct mtrr_pausing_state *state);
+extern void mtrr_resume_caching(struct mtrr_pausing_state state);
+
extern bool mtrr_var_range_msr_set(struct domain *d, struct mtrr_state *m,
uint32_t msr, uint64_t msr_content);
extern bool mtrr_fix_range_msr_set(struct domain *d, struct mtrr_state *m,
diff --git a/xen/arch/x86/include/asm/slaunch.h b/xen/arch/x86/include/asm/slaunch.h
index 3df7174b4b..459fc83388 100644
--- a/xen/arch/x86/include/asm/slaunch.h
+++ b/xen/arch/x86/include/asm/slaunch.h
@@ -23,8 +23,16 @@ struct slaunch_early_init_results
uint32_t slrt_pa;
} __packed;

+#ifdef CONFIG_SLAUNCH

/* Indicates an active Secure Launch boot. */
extern bool slaunch_active;

+#else
+/*
+ * This avoids `#ifdef CONFIG_SLAUNCH` around `if ( slaunch_active )` thanks to
+ * dead code elimination.
+ */
+static bool slaunch_active = false;
+#endif

/*

* Holds physical address of SLRT. Use slaunch_get_slrt() to access SLRT

diff --git a/xen/arch/x86/intel-txt.c b/xen/arch/x86/intel-txt.c
index 4a42abf8df..e0344d3421 100644
--- a/xen/arch/x86/intel-txt.c
+++ b/xen/arch/x86/intel-txt.c
@@ -8,10 +8,13 @@

#include <xen/bug.h>
#include <xen/init.h>
+#include <xen/kernel.h>
#include <xen/lib.h>
#include <xen/types.h>
#include <asm/e820.h>
#include <asm/intel-txt.h>
+#include <asm/msr.h>
+#include <asm/mtrr.h>
#include <asm/slaunch.h>

/*
@@ -111,3 +114,84 @@ void __init txt_reserve_mem_regions(void)
TXT_PRIV_CONFIG_REGS_BASE + TXT_CONFIG_SPACE_SIZE);
BUG_ON(!ok);
}
+
+void __init txt_restore_mtrrs(bool verbose)
+{
+ const struct slr_entry_hdr *entry;
+ const struct slr_entry_intel_info *intel_info;
+ uint64_t mtrr_cap, mtrr_def, base, mask;
+ unsigned int i;
+ unsigned int vcnt;
+ uint64_t def_type;
+ struct mtrr_pausing_state pausing_state;
+
+ mtrr_cap = rdmsr(MSR_MTRRcap);
+ mtrr_def = rdmsr(MSR_MTRRdefType);
+
+ vcnt = mtrr_cap & 0xFF;
+
+ if ( verbose )
+ {
+ printk("MTRRs set previously for SINIT ACM:\n");
+ printk(" MTRR cap: %"PRIx64" type: %"PRIx64"\n", mtrr_cap, mtrr_def);
+
+ for ( i = 0; i < vcnt; i++ )
+ {
+ base = rdmsr(MSR_IA32_MTRR_PHYSBASE(i));
+ mask = rdmsr(MSR_IA32_MTRR_PHYSMASK(i));
+
+ printk(" MTRR[%d]: base %"PRIx64" mask %"PRIx64"\n",
+ i, base, mask);
+ }
+ }
+
+ entry =
+ slr_next_entry_by_tag(slaunch_get_slrt(), NULL, SLR_ENTRY_INTEL_INFO);

+ intel_info = container_of(entry, const struct slr_entry_intel_info, hdr);
+

+ if ( vcnt != intel_info->saved_bsp_mtrrs.mtrr_vcnt )
+ {
+ printk("Bootloader saved %ld MTRR values, but there should be %d\n",
+ intel_info->saved_bsp_mtrrs.mtrr_vcnt, vcnt);
+ /* Choose the smaller one to be on the safe side. */
+ if ( intel_info->saved_bsp_mtrrs.mtrr_vcnt < vcnt )
+ vcnt = intel_info->saved_bsp_mtrrs.mtrr_vcnt;
+ }
+
+ def_type = intel_info->saved_bsp_mtrrs.default_mem_type;
+ mtrr_pause_caching(&pausing_state);
+
+ for ( i = 0; i < vcnt; i++ )
+ {
+ base = intel_info->saved_bsp_mtrrs.mtrr_pair[i].mtrr_physbase;
+ mask = intel_info->saved_bsp_mtrrs.mtrr_pair[i].mtrr_physmask;
+ wrmsr(MSR_IA32_MTRR_PHYSBASE(i), base);
+ wrmsr(MSR_IA32_MTRR_PHYSMASK(i), mask);
+ }
+
+ pausing_state.def_type = def_type;
+ mtrr_resume_caching(pausing_state);
+
+ if ( verbose )
+ {
+ printk("Restored MTRRs:\n");
+
+ /*
+ * If MTRRs are not enabled or WB is not the default, MTRRs won't be
+ * printed.
+ */
+ if ( !test_bit(11, &def_type) || (def_type & 0x7) == X86_MT_WB )
+ {
+ for ( i = 0; i < vcnt; i++ )
+ {
+ base = rdmsr(MSR_IA32_MTRR_PHYSBASE(i));
+ mask = rdmsr(MSR_IA32_MTRR_PHYSMASK(i));
+ printk(" MTRR[%d]: base %"PRIx64" mask %"PRIx64"\n",
+ i, base, mask);
+ }
+ }
+ }
+
+ /* Restore IA32_MISC_ENABLES */
+ wrmsr(MSR_IA32_MISC_ENABLE, intel_info->saved_misc_enable_msr);
+}
--
2.55.0

[Sergii Dmytruk]

From: Krystian Hebel <krystia...@3mdeb.com>

Make slaunch-tpm.c compile in early boot environment use it to measure
MBI in early 32b code without paging (gets triggered from head.S).

The fact of the measurement is not yet stored anywhere as there is no
code for TPM event log discovery and modification.

Signed-off-by: Krystian Hebel <krystia...@3mdeb.com>

Signed-off-by: Sergii Dmytruk <sergii....@3mdeb.com>
---

Notes:

v4: was part of "x86/tpm.c: code for early hashing and extending PCRs (for TPM1.2)"
v4: tpm_extend_mbi => slaunch_measure_mbi
v4: doesn't touch tpm.c, uses slaunch-tpm.c instead
v4: use `const multiboot2_fixed_t *` instead of `uint32_t *` for MBI

xen/arch/x86/boot/Makefile | 7 +-
xen/arch/x86/boot/head.S | 5 ++
xen/arch/x86/include/asm/slaunch-tpm.h | 7 ++
xen/arch/x86/include/asm/slaunch.h | 14 ++++
xen/arch/x86/slaunch-tpm.c | 112 +++++++++++++++++++++++++
xen/arch/x86/slaunch.c | 4 +
6 files changed, 148 insertions(+), 1 deletion(-)

diff --git a/xen/arch/x86/boot/Makefile b/xen/arch/x86/boot/Makefile
index 02f690d34a..b31c96be18 100644
--- a/xen/arch/x86/boot/Makefile
+++ b/xen/arch/x86/boot/Makefile
@@ -7,6 +7,7 @@ obj32 += reloc.32.o
obj32 += reloc-trampoline.32.o
ifeq ($(CONFIG_SLAUNCH),y)
obj32 += slaunch-early.32.o
+obj32 += slaunch-tpm-early.32.o
endif
obj32 += tpm-early.32.o

@@ -14,7 +15,7 @@ obj64 := reloc-trampoline.o

exports := cmdline_parse_early,reloc,reloc_trampoline32
ifeq ($(CONFIG_SLAUNCH),y)
-exports := $(exports),slaunch_early_init
+exports := $(exports),slaunch_early_init,slaunch_measure_mbi
endif

nocov-y += $(obj32) $(obj64)
@@ -39,6 +40,10 @@ $(obj)/%.32.o: $(src)/%.c FORCE

$(obj)/slaunch-early.32.o: XEN_CFLAGS += -D__EARLY_SLAUNCH__

+$(obj)/slaunch-tpm-early.32.o: XEN_CFLAGS += -D__EARLY_SLAUNCH__
+$(obj)/slaunch-tpm-early.32.o: $(src)/../slaunch-tpm.c FORCE
+ $(call if_changed_rule,cc_o_c)

+
$(obj)/tpm-early.32.o: XEN_CFLAGS += -D__EARLY_TPM__
$(obj)/tpm-early.32.o: $(src)/../tpm.c FORCE
$(call if_changed_rule,cc_o_c)

diff --git a/xen/arch/x86/boot/head.S b/xen/arch/x86/boot/head.S
index 700d1d850e..2c1a0f6306 100644
--- a/xen/arch/x86/boot/head.S
+++ b/xen/arch/x86/boot/head.S
@@ -539,6 +539,11 @@ __start:

pop sym_esi(slaunch_slrt) /* save physical address of SLRT for C

code */

+ mov sym_esi(slaunch_slrt), %edx /* physical SLRT address */
+ mov %ebx, %eax /* physical MBI address */
+ /* slaunch_measure_mbi(mbi/eax, slrt/edx) using fastcall. */
+ call slaunch_measure_mbi

+
/* Move magic number expected by Multiboot 2 to EAX and fall through. */

movl $MULTIBOOT2_BOOTLOADER_MAGIC, %eax
#endif
diff --git a/xen/arch/x86/include/asm/slaunch-tpm.h b/xen/arch/x86/include/asm/slaunch-tpm.h
index 68e9c8358a..79154f505b 100644
--- a/xen/arch/x86/include/asm/slaunch-tpm.h
+++ b/xen/arch/x86/include/asm/slaunch-tpm.h
@@ -16,4 +16,11 @@ struct slr_table;

void slaunch_find_log(const struct slr_table *slrt, paddr_t *evt_log,

uint32_t *evt_log_size);

+/*
+ * Log data is optional (pass in NULL and/or zero size to indicate its absence).
+ */
+void slaunch_hash_extend(unsigned int loc, unsigned int pcr, const uint8_t *buf,
+ unsigned int size, uint32_t type,
+ const uint8_t *log_data, unsigned int log_data_size);
+
#endif /* X86_SLAUNCH_TPM_H */
diff --git a/xen/arch/x86/include/asm/slaunch.h b/xen/arch/x86/include/asm/slaunch.h
index 459fc83388..65aab01f04 100644
--- a/xen/arch/x86/include/asm/slaunch.h
+++ b/xen/arch/x86/include/asm/slaunch.h
@@ -17,6 +17,20 @@
#include <xen/slr-table.h>
#include <xen/types.h>

+#define DRTM_LOC 2
+#define DRTM_CODE_PCR 17
+#define DRTM_DATA_PCR 18
+
+/*
+ * Secure Launch event log entry types. The TXT specification defines the base
+ * event value as 0x400 for DRTM values, use it regardless of the DRTM for
+ * consistency.
+ */
+#define DLE_EVTYPE_BASE 0x400
+#define DLE_EVTYPE_SLAUNCH (DLE_EVTYPE_BASE + 0x102)
+#define DLE_EVTYPE_SLAUNCH_START (DLE_EVTYPE_BASE + 0x103)
+#define DLE_EVTYPE_SLAUNCH_END (DLE_EVTYPE_BASE + 0x104)
+
struct slaunch_early_init_results
{
uint32_t mbi_pa;
diff --git a/xen/arch/x86/slaunch-tpm.c b/xen/arch/x86/slaunch-tpm.c
index f59170594d..21dec67dca 100644
--- a/xen/arch/x86/slaunch-tpm.c
+++ b/xen/arch/x86/slaunch-tpm.c
@@ -2,13 +2,71 @@
/*

* Slaunch functions related to TPM.

*
+ * This file is built twice:

+ * 1. For early 32b mode without paging when it also provides
+ * slaunch_measure_mbi() to be called from assembly.
+ * 2. For 64b code.
+ *

* Copyright (c) 2022-2026 3mdeb Sp. z o.o. All rights reserved.

*/

+#include <xen/compiler.h>
+#include <xen/lib.h>
#include <xen/macros.h>
+#include <xen/multiboot2.h>
+#include <xen/sha1.h>
+#include <xen/sha2.h>
#include <xen/slr-table.h>
#include <xen/types.h>

+#include <asm/intel-txt.h>
+#include <asm/slaunch.h>
+#include <asm/slaunch-tpm.h>
+#include <asm/tpm.h>
+#include <asm/tpm2.h>
+
+#ifdef __EARLY_SLAUNCH__

+
+#ifdef __va
+#error "__va defined in non-paged mode!"
+#endif
+
+#define __va(x) _p(x)
+

+static uint32_t slrt_location;
+
+/*

+ * The code is being compiled as a standalone binary without linking to any
+ * other part of Xen. Providing implementation of builtin functions in this
+ * case is necessary if compiler chooses to not use an inline builtin.
+ */

+void *(memset)(void *s, int c, size_t n)
+{
+ uint8_t *d = s;

+
+ while ( n-- )

+ *d++ = c;
+
+ return s;
+}
+
+struct slr_table *slaunch_get_slrt(void)
+{
+ return _p(slrt_location);
+}
+
+void asmlinkage slaunch_measure_mbi(const multiboot2_fixed_t *mbi,
+ uint32_t slrt_pa)
+{
+ /* Need this to implement slaunch_get_slrt() for early TPM code. */
+ slrt_location = slrt_pa;
+
+ slaunch_hash_extend(DRTM_LOC, DRTM_DATA_PCR, (const uint8_t *)mbi,
+ mbi->total_size, DLE_EVTYPE_SLAUNCH, NULL, 0);
+}
+
+#endif /* __EARLY_SLAUNCH__ */
+

void slaunch_find_log(const struct slr_table *slrt, paddr_t *evt_log,

uint32_t *evt_log_size)
{
@@ -34,3 +92,57 @@ void slaunch_find_log(const struct slr_table *slrt, paddr_t *evt_log,
*evt_log_size = 0;
}
}
+
+void slaunch_hash_extend(unsigned int loc, unsigned int pcr, const uint8_t *buf,
+ unsigned int size, uint32_t type,
+ const uint8_t *log_data, unsigned int log_data_size)
+{
+ paddr_t evt_log_paddr;
+ uint32_t evt_log_size;
+ struct tpm_log_hashes log_hashes;
+ uint8_t discarded_digests[SHA2_256_DIGEST_SIZE];
+ uint32_t rc;
+
+ slaunch_find_log(slaunch_get_slrt(), &evt_log_paddr, &evt_log_size);

+
+ if ( tpm_is_tpm1() )
+ {

+ log_hashes = (struct tpm_log_hashes) {
+ .count = 1,
+ .hashes = {
+ {
+ .alg = TPM_ALG_SHA1,
+ .size = SHA1_DIGEST_SIZE,
+ .data = discarded_digests,
+ },
+ },
+ };
+ }
+ else
+ {
+ log_hashes = (struct tpm_log_hashes) {
+ .count = 2,
+ .hashes = {
+ {
+ .alg = TPM_ALG_SHA1,
+ .size = SHA1_DIGEST_SIZE,
+ .data = discarded_digests,
+ },
+ {
+ .alg = TPM_ALG_SHA256,
+ .size = SHA2_256_DIGEST_SIZE,
+ .data = discarded_digests,
+ },
+ },
+ };
+ }
+
+ rc = tpm_hash_extend(loc, pcr, buf, size, &log_hashes);
+ if (rc != 0)
+ {
+#ifndef __EARLY_SLAUNCH__
+ printk(XENLOG_ERR "Extending PCR-%u failed with an error: 0x%08x\n",
+ pcr, rc);
+#endif

+ }
+}
diff --git a/xen/arch/x86/slaunch.c b/xen/arch/x86/slaunch.c

index ba1ba61c47..83dce3d57d 100644
--- a/xen/arch/x86/slaunch.c
+++ b/xen/arch/x86/slaunch.c
@@ -18,6 +18,7 @@
#include <asm/setup.h>
#include <asm/slaunch.h>
#include <asm/slaunch-tpm.h>
+#include <asm/tpm.h>

/*
* These variables are assigned to by the code near Xen's entry point.

@@ -78,6 +79,9 @@ void __init slaunch_map_mem_regions(void)
paddr_t evt_log_addr;
uint32_t evt_log_size;

+ rc = slaunch_map_l2(TPM_MMIO_BASE, TPM_MMIO_SIZE);

+ BUG_ON(rc != 0);
+

/* Vendor-specific part. */
txt_map_mem_regions();

--
2.55.0

[Sergii Dmytruk]

Instead of storing hashing result to stack variables, a TPM event log is discovered in an Slaunch-specific way, extended with an additional entry and that entry is filled with digests.

Signed-off-by: Krystian Hebel <krystia...@3mdeb.com>
Signed-off-by: Szymon Acedański <ac...@invisiblethingslab.com>
Assisted-by: Claude:claude-opus-4-7

Signed-off-by: Sergii Dmytruk <sergii....@3mdeb.com>
---

Notes:

v4: was "x86/tpm.c: implement event log for TPM2.0"
v4: part of it as in "x86/tpm.c: code for early hashing and extending PCRs (for TPM1.2)"
v4: TPM event log code was part of tpm.c changes, now in slaunch-tpm.c
v4: fixed comment on txt_ext_data_element::size and finding log element (worked because it was first)
v4: provide list of hashes even in the absence of event log to extend PCRs

xen/arch/x86/include/asm/intel-txt.h | 69 ++++++++++
xen/arch/x86/slaunch-tpm.c | 188 +++++++++++++++++++++++----
2 files changed, 232 insertions(+), 25 deletions(-)

diff --git a/xen/arch/x86/include/asm/intel-txt.h b/xen/arch/x86/include/asm/intel-txt.h
index 406929fac2..8bcca20d6e 100644
--- a/xen/arch/x86/include/asm/intel-txt.h
+++ b/xen/arch/x86/include/asm/intel-txt.h
@@ -71,6 +71,8 @@
#include <xen/multiboot2.h>
#include <xen/slr-table.h>

+#include <asm/tpm1.h>

+
/* Need to differentiate between pre- and post paging enabled. */
#ifdef __EARLY_SLAUNCH__
#include <xen/macros.h>

@@ -200,6 +202,52 @@ struct txt_sinit_mle_data {

/* Ext Data Elements */

} __packed;

+struct txt_ev_log_container_12 {
+ char Signature[20]; /* "TXT Event Container", null-terminated */
+ uint8_t Reserved[12];
+ uint8_t ContainerVerMajor;
+ uint8_t ContainerVerMinor;
+ uint8_t PCREventVerMajor;
+ uint8_t PCREventVerMinor;
+ uint32_t ContainerSize; /* Allocated size */
+ uint32_t PCREventsOffset;
+ uint32_t NextEventOffset;
+ struct TPM12_PCREvent PCREvents[];
+};
+
+/* Types of extended data. */
+#define TXT_HEAP_EXTDATA_TYPE_END 0
+#define TXT_HEAP_EXTDATA_TYPE_BIOS_SPEC_VER 1
+#define TXT_HEAP_EXTDATA_TYPE_ACM 2
+#define TXT_HEAP_EXTDATA_TYPE_STM 3
+#define TXT_HEAP_EXTDATA_TYPE_CUSTOM 4
+#define TXT_HEAP_EXTDATA_TYPE_MADT 6
+#define TXT_HEAP_EXTDATA_TYPE_EVENT_LOG_POINTER2_1 8
+#define TXT_HEAP_EXTDATA_TYPE_MCFG 9
+#define TXT_HEAP_EXTDATA_TYPE_TPR_REQ 13
+#define TXT_HEAP_EXTDATA_TYPE_DTPR 14
+#define TXT_HEAP_EXTDATA_TYPE_CEDT 15
+
+/*
+ * Self-describing data structure that is used for extensions to TXT heap
+ * tables.
+ */
+struct txt_ext_data_element {
+ uint32_t type; /* One of TXT_HEAP_EXTDATA_TYPE_*. */
+ uint32_t size; /* Size of the whole element (header + data), in bytes. */
+ uint8_t data[0];
+} __packed;
+
+/*
+ * Extended data describing TPM 2.0 log.
+ */
+struct heap_event_log_pointer_element2_1 {
+ uint64_t physical_address;
+ uint32_t allocated_event_container_size;
+ uint32_t first_record_offset;
+ uint32_t next_record_offset;
+} __packed;
+
/*

* Functions to extract data from the Intel TXT Heap Memory.

*
@@ -268,6 +316,27 @@ static inline void *txt_init(void)
return txt_heap;
}

+/*
+ * Find the given element in the TXT heap extended data.
+ */
+static inline struct txt_ext_data_element *
+txt_find_ext_data_element(struct txt_os_sinit_data *os_sinit, uint32_t type)
+{
+ struct txt_ext_data_element *ext_elem;
+
+ ext_elem = (void *)os_sinit + sizeof(struct txt_os_sinit_data);
+
+ while ( ext_elem->type != TXT_HEAP_EXTDATA_TYPE_END )
+ {
+ if ( ext_elem->type == type )
+ return ext_elem;
+
+ ext_elem = (void *)ext_elem + ext_elem->size;

+ }
+
+ return NULL;
+}
+

static inline bool is_in_pmr(const struct txt_os_sinit_data *os_sinit,

uint64_t base, uint32_t size, bool check_high)

{
diff --git a/xen/arch/x86/slaunch-tpm.c b/xen/arch/x86/slaunch-tpm.c
index 21dec67dca..e3b7341cc5 100644
--- a/xen/arch/x86/slaunch-tpm.c
+++ b/xen/arch/x86/slaunch-tpm.c
@@ -67,6 +67,136 @@ void asmlinkage slaunch_measure_mbi(const multiboot2_fixed_t *mbi,

#endif /* __EARLY_SLAUNCH__ */

+static struct tpm_log_hashes
+create_log_event12(struct txt_ev_log_container_12 *evt_log,
+ uint32_t evt_log_size, uint32_t pcr, uint32_t type,
+ const uint8_t *data, unsigned data_size)
+{
+ struct tpm_log_hashes log_hashes = {0};
+
+ struct TPM12_PCREvent *new_entry;
+
+ if (evt_log == NULL)
+ return log_hashes;
+
+ new_entry = (void *)evt_log + evt_log->NextEventOffset;
+
+ /*
+ * Check if there is enough space left for new entry.
+ * Note: it is possible to introduce a gap in event log if entry with big
+ * data_size is followed by another entry with smaller data. Maybe we should
+ * cap the event log size in such case?
+ */
+ if ( evt_log->NextEventOffset + sizeof(struct TPM12_PCREvent) + data_size >
+ evt_log_size )
+ return log_hashes;
+
+ evt_log->NextEventOffset += sizeof(struct TPM12_PCREvent) + data_size;
+
+ new_entry->PCRIndex = pcr;
+ new_entry->Type = type;
+ new_entry->Size = data_size;
+
+ if ( data != NULL && data_size > 0 )
+ memcpy(new_entry->Data, data, data_size);
+
+ log_hashes.count = 1;
+ log_hashes.hashes[0].alg = TPM_ALG_SHA1;
+ log_hashes.hashes[0].size = SHA1_DIGEST_SIZE;
+ log_hashes.hashes[0].data = new_entry->Digest;
+
+ return log_hashes;
+}
+
+static struct heap_event_log_pointer_element2_1 *
+find_evt_log_ext_data(struct tpm2_spec_id_event *evt_log)
+{
+ struct txt_os_sinit_data *os_sinit;
+ struct txt_ext_data_element *ext_data;
+
+ os_sinit = txt_start(__va(txt_read(TXTCR_HEAP_BASE)), TXT_OS2SINIT);
+ ext_data = txt_find_ext_data_element(os_sinit,
+ TXT_HEAP_EXTDATA_TYPE_EVENT_LOG_POINTER2_1);
+ if ( ext_data == NULL )
+ return NULL;
+
+ return (struct heap_event_log_pointer_element2_1 *)ext_data->data;
+}
+
+static struct tpm_log_hashes
+create_log_event20(struct tpm2_spec_id_event *evt_log, uint32_t evt_log_size,
+ uint32_t pcr, uint32_t type, const uint8_t *data,
+ unsigned data_size)
+{
+ struct tpm_log_hashes log_hashes = {0};
+
+ struct heap_event_log_pointer_element2_1 *log_ext_data;
+ struct tpm2_pcr_event_header *new_entry;
+ uint32_t entry_size;
+ unsigned i;
+ uint8_t *p;
+
+ if (evt_log == NULL)
+ return log_hashes;
+
+ log_ext_data = find_evt_log_ext_data(evt_log);
+ if ( log_ext_data == NULL )
+ return log_hashes;
+
+ entry_size = sizeof(*new_entry);
+ for ( i = 0; i < evt_log->digestCount; ++i )
+ {
+ entry_size += sizeof(uint16_t); /* hash type */
+ entry_size += evt_log->digestSizes[i].digestSize;
+ }
+ entry_size += sizeof(uint32_t); /* data size field */
+ entry_size += data_size;
+
+ /*
+ * Check if there is enough space left for new entry.
+ * Note: it is possible to introduce a gap in event log if entry with big
+ * data_size is followed by another entry with smaller data. Maybe we should
+ * cap the event log size in such case?
+ */
+ if ( log_ext_data->next_record_offset + entry_size > evt_log_size )
+ return log_hashes;
+
+ new_entry = (void *)evt_log + log_ext_data->next_record_offset;
+ log_ext_data->next_record_offset += entry_size;
+
+ new_entry->pcrIndex = pcr;
+ new_entry->eventType = type;
+ new_entry->digestCount = evt_log->digestCount;
+
+ p = &new_entry->digests[0];
+ for ( i = 0; i < evt_log->digestCount; ++i )
+ {
+ uint16_t alg = evt_log->digestSizes[i].algId;
+ uint16_t size = evt_log->digestSizes[i].digestSize;
+
+ *(uint16_t *)p = alg;

+ p += sizeof(uint16_t);
+

+ log_hashes.hashes[i].alg = alg;
+ log_hashes.hashes[i].size = size;
+ log_hashes.hashes[i].data = p;
+ p += size;
+
+ /* This is called "OneDigest" in TXT Software Development Guide. */
+ memset(log_hashes.hashes[i].data, 0, size);
+ log_hashes.hashes[i].data[0] = 1;
+ }
+ log_hashes.count = evt_log->digestCount;
+
+ *(uint32_t *)p = data_size;
+ p += sizeof(uint32_t);
+
+ if ( data != NULL && data_size > 0 )
+ memcpy(p, data, data_size);
+
+ return log_hashes;
+}

+
void slaunch_find_log(const struct slr_table *slrt, paddr_t *evt_log,
uint32_t *evt_log_size)
{

@@ -99,42 +229,50 @@ void slaunch_hash_extend(unsigned int loc, unsigned int pcr, const uint8_t *buf,
{
paddr_t evt_log_paddr;
uint32_t evt_log_size;
- struct tpm_log_hashes log_hashes;
uint8_t discarded_digests[SHA2_256_DIGEST_SIZE];
+ struct tpm_log_hashes log_hashes;
uint32_t rc;

slaunch_find_log(slaunch_get_slrt(), &evt_log_paddr, &evt_log_size);

if ( tpm_is_tpm1() )
{
- log_hashes = (struct tpm_log_hashes) {
- .count = 1,
- .hashes = {
- {
- .alg = TPM_ALG_SHA1,
- .size = SHA1_DIGEST_SIZE,
- .data = discarded_digests,
- },
- },
- };
+ struct txt_ev_log_container_12 *evt_log = __va(evt_log_paddr);
+
+ log_hashes = create_log_event12(evt_log, evt_log_size, pcr, type,
+ log_data, log_data_size);
}
else
{
- log_hashes = (struct tpm_log_hashes) {
- .count = 2,
- .hashes = {
- {
- .alg = TPM_ALG_SHA1,
- .size = SHA1_DIGEST_SIZE,
- .data = discarded_digests,
- },
- {
- .alg = TPM_ALG_SHA256,
- .size = SHA2_256_DIGEST_SIZE,
- .data = discarded_digests,
+ struct tpm2_spec_id_event *evt_log = __va(evt_log_paddr);
+
+ log_hashes = create_log_event20(evt_log, evt_log_size, pcr, type,
+ log_data, log_data_size);
+
+ if ( log_hashes.count == 0 )
+ {
+ /*
+ * Because TPM2 supports multiple PCR banks, the list of digests is
+ * also used to indicate which banks to extend. Thus avoid passing
+ * an empty list of digests to have a chance of something being
+ * extended even without event log.
+ */

+ log_hashes = (struct tpm_log_hashes) {
+ .count = 2,
+ .hashes = {
+ {
+ .alg = TPM_ALG_SHA1,
+ .size = SHA1_DIGEST_SIZE,
+ .data = discarded_digests,
+ },
+ {
+ .alg = TPM_ALG_SHA256,
+ .size = SHA2_256_DIGEST_SIZE,
+ .data = discarded_digests,
+ },

},
- },
- };

+ };
+ }
}

rc = tpm_hash_extend(loc, pcr, buf, size, &log_hashes);

--
2.55.0

[Sergii Dmytruk]

From: Michał Żygowski <michal....@3mdeb.com>

Check whther IA32_FEATURE_CONTROL has the proper bits enabled to run
VMX in SMX when slaunch is active.

Signed-off-by: Michał Żygowski <michal....@3mdeb.com>
Signed-off-by: Sergii Dmytruk <sergii....@3mdeb.com>

Acked-by: Jan Beulich <jbeu...@suse.com>
---

Notes:
v4: added Acked-by

xen/arch/x86/hvm/vmx/vmcs.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/xen/arch/x86/hvm/vmx/vmcs.c b/xen/arch/x86/hvm/vmx/vmcs.c
index 8e52ef4d49..3c5dfd7c1b 100644
--- a/xen/arch/x86/hvm/vmx/vmcs.c
+++ b/xen/arch/x86/hvm/vmx/vmcs.c
@@ -30,6 +30,7 @@
#include <asm/msr.h>
#include <asm/processor.h>
#include <asm/shadow.h>
+#include <asm/slaunch.h>
#include <asm/spec_ctrl.h>
#include <asm/tboot.h>
#include <asm/xstate.h>
@@ -742,7 +743,7 @@ static int _vmx_cpu_up(bool bsp)
bios_locked = !!(eax & IA32_FEATURE_CONTROL_LOCK);
if ( bios_locked )
{
- if ( !(eax & (tboot_in_measured_env()
+ if ( !(eax & (tboot_in_measured_env() || slaunch_active
? IA32_FEATURE_CONTROL_ENABLE_VMXON_INSIDE_SMX
: IA32_FEATURE_CONTROL_ENABLE_VMXON_OUTSIDE_SMX)) )
{
--
2.55.0

[Sergii Dmytruk]

From: Krystian Hebel <krystia...@3mdeb.com>

This is made as the first step of making parallel AP bring-up possible.
It should be enough for pre-C code.

Parallel AP bring-up is necessary because TXT by design releases all APs
at once. In addition to that it reduces number of IPIs (and more
importantly, delays between them) required to start all logical
processors. This results in significant reduction of boot time, even
when DRTM is not used, with performance gain growing with the number of
logical CPUs.

Signed-off-by: Krystian Hebel <krystia...@3mdeb.com>

Signed-off-by: Sergii Dmytruk <sergii....@3mdeb.com>
---

Notes:

v4: better comments in boot/trampoline.S
v4: use %ebp instead of %esp to pass data to boot/x86_64.S
v4: use `nr_cpu_ids(%rip)` instead of `$NR_CPUS` in boot/x86_64.S
v4: L_stack_set => L_after_stack_setup
v4: __ASSEMBLY__ => __ASSEMBLER__

xen/arch/x86/boot/head.S | 1 +
xen/arch/x86/boot/trampoline.S | 23 +++++++++++++++++++++
xen/arch/x86/boot/x86_64.S | 31 +++++++++++++++++++++++++++-
xen/arch/x86/include/asm/apicdef.h | 4 ++++
xen/arch/x86/include/asm/msr-index.h | 3 +++
xen/arch/x86/setup.c | 7 +++++++
6 files changed, 68 insertions(+), 1 deletion(-)

diff --git a/xen/arch/x86/boot/head.S b/xen/arch/x86/boot/head.S
index 2c1a0f6306..ff46579904 100644
--- a/xen/arch/x86/boot/head.S
+++ b/xen/arch/x86/boot/head.S
@@ -8,6 +8,7 @@

#include <asm/page.h>
#include <asm/processor.h>
#include <asm/msr-index.h>

+#include <asm/apicdef.h>
#include <asm/cpufeature.h>
#include <asm/trampoline.h>

diff --git a/xen/arch/x86/boot/trampoline.S b/xen/arch/x86/boot/trampoline.S
index a92e399fbe..9306c1bb76 100644
--- a/xen/arch/x86/boot/trampoline.S
+++ b/xen/arch/x86/boot/trampoline.S
@@ -71,6 +71,29 @@ trampoline_protmode_entry:
mov $X86_CR4_PAE,%ecx
mov %ecx,%cr4

+ /*
+ * Get APIC ID while we're in non-paged mode to later derive Xen CPU
+ * index and determine CPU-specific stack. Start by checking if x2APIC
+ * is enabled.
+ */
+ mov $MSR_APIC_BASE, %ecx
+ rdmsr
+ test $APIC_BASE_EXTD, %eax
+ jnz .Lx2apic
+
+ /* Not x2APIC, read APIC ID from MMIO. */
+ and $APIC_BASE_ADDR_MASK, %eax
+ mov APIC_ID(%eax), %eax
+ shr $24, %eax
+ jmp 1f
+
+.Lx2apic:
+ mov $(MSR_X2APIC_FIRST + (APIC_ID >> MSR_X2APIC_SHIFT)), %ecx
+ rdmsr
+1:
+ /* The value of the APIC ID will be consumed in __high_start. */
+ mov %eax, %ebp
+
/* Load pagetable base register. */
mov $sym_offs(idle_pg_table),%eax
add bootsym_rel(trampoline_xen_phys_start,4,%eax)
diff --git a/xen/arch/x86/boot/x86_64.S b/xen/arch/x86/boot/x86_64.S
index 9705d03f84..19f3062a7b 100644
--- a/xen/arch/x86/boot/x86_64.S
+++ b/xen/arch/x86/boot/x86_64.S
@@ -11,7 +11,36 @@ ENTRY(__high_start)
mov %ecx,%gs
mov %ecx,%ss

- mov stack_start(%rip),%rsp
+ /* %ebx is set to non-zero in trampoline.S to indicate an AP. */
+ test %ebx, %ebx
+ cmovz stack_start(%rip), %rsp
+ jz .L_after_stack_setup
+
+ /*
+ * APs only: get stack base from APIC ID saved to %ebp in trampoline.S.
+ */
+ mov $-1, %rax
+ lea x86_cpu_to_apicid(%rip), %rcx
+1:
+ inc %rax
+ cmp nr_cpu_ids(%rip), %eax
+ jb 2f
+ hlt
+2:
+ cmp %ebp, (%rcx, %rax, 4)
+ jne 1b
+
+ /* %eax is now Xen CPU index. */
+ lea stack_base(%rip), %rcx
+ mov (%rcx, %rax, 8), %rsp
+
+ test %rsp, %rsp
+ jnz 1f
+ hlt
+1:
+ add $(STACK_SIZE - CPUINFO_sizeof), %rsp
+
+.L_after_stack_setup:

/* Reset EFLAGS (subsumes CLI and CLD). */
pushq $0
diff --git a/xen/arch/x86/include/asm/apicdef.h b/xen/arch/x86/include/asm/apicdef.h
index 112c1dc613..7a09d08b91 100644
--- a/xen/arch/x86/include/asm/apicdef.h
+++ b/xen/arch/x86/include/asm/apicdef.h
@@ -120,6 +120,10 @@

#define MAX_IO_APICS 128

+#ifndef __ASSEMBLER__
+
extern bool x2apic_enabled;

+#endif /* !__ASSEMBLER__ */
+

#endif
diff --git a/xen/arch/x86/include/asm/msr-index.h b/xen/arch/x86/include/asm/msr-index.h
index ad1c6c97f8..0900e21811 100644
--- a/xen/arch/x86/include/asm/msr-index.h
+++ b/xen/arch/x86/include/asm/msr-index.h
@@ -186,6 +186,9 @@
#define MSR_X2APIC_FIRST 0x00000800
#define MSR_X2APIC_LAST 0x000008ff

+/* MSR offset can be obtained by shifting MMIO offset this number of bits to the right. */
+#define MSR_X2APIC_SHIFT 4
+
#define MSR_X2APIC_TPR 0x00000808
#define MSR_X2APIC_PPR 0x0000080a
#define MSR_X2APIC_EOI 0x0000080b
diff --git a/xen/arch/x86/setup.c b/xen/arch/x86/setup.c
index 5494fa1621..fbc44b0174 100644
--- a/xen/arch/x86/setup.c
+++ b/xen/arch/x86/setup.c
@@ -2141,6 +2141,7 @@ void asmlinkage __init noreturn __start_xen(void)
*/
if ( !pv_shim )
{
+ /* Separate loop to make parallel AP bringup possible. */
for_each_present_cpu ( i )
{
/* Set up cpu_to_node[]. */
@@ -2148,6 +2149,12 @@ void asmlinkage __init noreturn __start_xen(void)
/* Set up node_to_cpumask based on cpu_to_node[]. */
numa_add_cpu(i);

+ if ( stack_base[i] == NULL )
+ stack_base[i] = cpu_alloc_stack(i);
+ }
+
+ for_each_present_cpu ( i )
+ {
if ( (park_offline_cpus || num_online_cpus() < max_cpus) &&
!cpu_online(i) )
{
--
2.55.0

[Sergii Dmytruk]

From: Krystian Hebel <krystia...@3mdeb.com>

On Intel TXT, APs are started in one of two ways, depending on ACM
which reports it in its information table. In both cases, all APs are
started simultaneously after BSP requests them to do so. Two possible
ways are:
- GETSEC[WAKEUP] instruction,
- MONITOR address.

GETSEC[WAKEUP] requires versions >= 7 of SINIT to MLE Data, but there is
no clear mapping of that version with regard to processor family and
it's not known which CPUs actually use it. It could have been designed
for TXT support on CPUs that lack MONITOR/MWAIT, because GETSEC[WAKEUP]
seems to be more complicated, in software and hardware alike.

This patch implements only MONITOR approach, GETSEC[WAKEUP] support will
be added later once more details and means of testing are available and
if there is a practical need for it.

With this patch, every AP goes through assembly part, and only when in
start_secondary() in C they re-enter MONITOR/MWAIT iff they are not the
AP that was asked to boot. The same address is reused for simplicity,
and on next wakeup call APs don't have to go through assembly part
again (GDT, paging, stack setting).

Signed-off-by: Krystian Hebel <krystia...@3mdeb.com>
Signed-off-by: Sergii Dmytruk <sergii....@3mdeb.com>

Signed-off-by: Szymon Acedański <ac...@invisiblethingslab.com>
Assisted-by: Claude:claude-opus-4-6
Signed-off-by: Michał Iwanicki <michal....@3mdeb.com>
---

Notes:
v4: replace TXT_AP_BOOT_CS and TXT_AP_BOOT_DS with trampoline_gdt_txt and computing CS
v4: make APs call C from __high_start to synchronize with BSP
v4: recheck condition between `monitor` and `mwait` instructions
v4: write to wakeup address only once (all APs are woken up at once)
v4: make JOIN variable static as it's not read synchronously
v4: when an AP waits for a wakeup, monitor the variable that's expected to change

xen/arch/x86/boot/trampoline.S | 19 ++++++-
xen/arch/x86/boot/x86_64.S | 24 ++++++++-
xen/arch/x86/include/asm/intel-txt.h | 5 ++
xen/arch/x86/include/asm/processor.h | 1 +
xen/arch/x86/smpboot.c | 75 ++++++++++++++++++++++++++++
xen/arch/x86/x86_64/asm-offsets.c | 3 ++
6 files changed, 125 insertions(+), 2 deletions(-)

diff --git a/xen/arch/x86/boot/trampoline.S b/xen/arch/x86/boot/trampoline.S
index 9306c1bb76..4208bd75b8 100644
--- a/xen/arch/x86/boot/trampoline.S
+++ b/xen/arch/x86/boot/trampoline.S
@@ -58,6 +58,16 @@ GLOBAL(entry_SIPI16)
ljmpl $BOOT_CS32,$bootsym_rel(trampoline_protmode_entry,6)

.code32
+GLOBAL(txt_ap_entry)
+ /*
+ * APs enter here in protected mode without paging. GDT is set in JOIN
+ * structure, it points to trampoline_gdt. Interrupts are disabled by
+ * TXT (including NMI and SMI), so IDT doesn't matter at this point.
+ * The only missing point is telling that we are AP by saving non-zero
+ * value in EBX.
+ */
+ mov $1, %ebx
+
trampoline_protmode_entry:
/* Set up a few descriptors: on entry only CS is guaranteed good. */
mov $BOOT_DS,%eax
@@ -145,7 +155,7 @@ start64:
.word 0
idt_48: .word 0, 0, 0 # base = limit = 0

-trampoline_gdt:
+GLOBAL(trampoline_gdt)
.word 0 /* 0x0000: unused (reused for GDTR) */
gdt_48:
.word .Ltrampoline_gdt_end - trampoline_gdt - 1
@@ -156,6 +166,13 @@ gdt_48:
.quad 0x00cf93000000ffff /* 0x0018: ring 0 data */
.quad 0x00009b000000ffff /* 0x0020: real-mode code @ BOOT_TRAMPOLINE */
.quad 0x000093000000ffff /* 0x0028: real-mode data @ BOOT_TRAMPOLINE */
+ /*
+ * Intel TXT requires these two in exact order. This isn't compatible
+ * with the order required by syscall, so we have duplicated entries...
+ */
+GLOBAL(trampoline_gdt_txt)
+ .quad 0x00cf9b000000ffff /* 0x0030: ring 0 code, 32-bit mode */
+ .quad 0x00cf93000000ffff /* 0x0038: ring 0 data */
.Ltrampoline_gdt_end:

/* Relocations for trampoline Real Mode segments. */
diff --git a/xen/arch/x86/boot/x86_64.S b/xen/arch/x86/boot/x86_64.S
index 19f3062a7b..886960c22f 100644
--- a/xen/arch/x86/boot/x86_64.S
+++ b/xen/arch/x86/boot/x86_64.S
@@ -30,7 +30,10 @@ ENTRY(__high_start)

cmp %ebp, (%rcx, %rax, 4)

jne 1b

- /* %eax is now Xen CPU index. */
+ mov %ebp, %edx
+
+ /* %eax is now Xen CPU index, %edx is APIC ID. */
+
lea stack_base(%rip), %rcx

mov (%rcx, %rax, 8), %rsp

@@ -40,6 +43,25 @@ ENTRY(__high_start)
1:

add $(STACK_SIZE - CPUINFO_sizeof), %rsp

+ /*
+ * TXT AP gate.
+ *
+ * In TXT boot, SINIT releases all APs at once and they race into
+ * __high_start in parallel. We serialize APs initialization here
+ * to force them waking up in order expected by the BSP.
+ *
+ * The gate must be placed before STACK_CPUINFO_FIELD(cr4) is written
+ * below: for each AP, the BSP memsets that AP's cpu_info struct in
+ * cpu_smpboot_alloc() just before releasing it through the gate, so
+ * anything written earlier would be clobbered.
+ *
+ * In non-TXT boot, APs wake one-by-one via SIPI.
+ */
+ cmpl $ASM_AP_BOOT_TXT, ap_boot_method(%rip)
+ jne .L_after_stack_setup
+ mov %edx, %edi
+ call txt_ap_gate
+

.L_after_stack_setup:

/* Reset EFLAGS (subsumes CLI and CLD). */

diff --git a/xen/arch/x86/include/asm/intel-txt.h b/xen/arch/x86/include/asm/intel-txt.h
index 8bcca20d6e..eb15bf68ad 100644
--- a/xen/arch/x86/include/asm/intel-txt.h
+++ b/xen/arch/x86/include/asm/intel-txt.h
@@ -83,6 +83,11 @@
#define _txt(x) __va(x)
#endif

+extern char txt_ap_entry[];
+extern uint64_t trampoline_gdt[];
+/* Points at CS selector for TXT, DS selector follows. */
+extern uint64_t trampoline_gdt_txt[];
+
/*

* Always use private space as some of registers are either read-only or not

* present in public space.

diff --git a/xen/arch/x86/include/asm/processor.h b/xen/arch/x86/include/asm/processor.h
index 8ca6799a81..2c6e7b772f 100644
--- a/xen/arch/x86/include/asm/processor.h
+++ b/xen/arch/x86/include/asm/processor.h
@@ -436,6 +436,7 @@ void set_in_pb_opt_ctrl(uint32_t mask, uint32_t val);
enum ap_boot_method {
AP_BOOT_NORMAL,
AP_BOOT_SKINIT,
+ AP_BOOT_TXT,
};
extern enum ap_boot_method ap_boot_method;

diff --git a/xen/arch/x86/smpboot.c b/xen/arch/x86/smpboot.c
index 84e9e4beed..cdad60d5e4 100644
--- a/xen/arch/x86/smpboot.c
+++ b/xen/arch/x86/smpboot.c
@@ -30,6 +30,7 @@
#include <asm/flushtlb.h>
#include <asm/guest.h>
#include <asm/idt.h>
+#include <asm/intel-txt.h>
#include <asm/io_apic.h>
#include <asm/irq-vectors.h>
#include <asm/mc146818rtc.h>
@@ -38,6 +39,7 @@
#include <asm/mtrr.h>
#include <asm/prot-key.h>
#include <asm/setup.h>
+#include <asm/slaunch.h>
#include <asm/spec_ctrl.h>
#include <asm/stubs.h>
#include <asm/tboot.h>
@@ -239,6 +241,32 @@ static void smp_callin(void)
cpu_relax();
}

+/*
+ * ACPI ID of the AP to be released by txt_ap_gate() next. Gets set in
+ * wake_ap_in_txt() after which do_boot_cpu() waits for the AP to initialize
+ * itself.
+ */
+static int txt_booting_apicid;
+
+void asmlinkage txt_ap_gate(int apicid)
+{
+ uint64_t misc_enable;
+
+ /* TXT released us with MONITOR disabled in IA32_MISC_ENABLE. */
+ misc_enable = rdmsr(MSR_IA32_MISC_ENABLE);
+ wrmsr(MSR_IA32_MISC_ENABLE,
+ misc_enable | MSR_IA32_MISC_ENABLE_MONITOR_ENABLE);
+
+ while ( txt_booting_apicid != apicid )
+ {
+ asm volatile ( "monitor"
+ :: "a"(&txt_booting_apicid), "c"(0), "d"(0) : "memory" );
+ if ( txt_booting_apicid == apicid )
+ break;
+ asm volatile ( "mwait" :: "a"(0), "c"(0) );
+ }
+}
+
/* CPUs for which sibling maps can be computed. */
static cpumask_t cpu_sibling_setup_map;

@@ -417,6 +445,37 @@ void asmlinkage start_secondary(void)
startup_cpu_idle_loop();
}

+static int wake_ap_in_txt(int phys_apicid)
+{
+ static uint32_t join[4];
+
+ txt_booting_apicid = phys_apicid;
+ smp_mb();
+
+ /*
+ * All APs are released at the same time on the first write to wakeup
+ * address, which happens on the first invocation. Because the write isn't
+ * handled synchronously, the JOIN structure must outlive this function.
+ */
+ if (join[0] == 0)
+ {
+ const struct txt_sinit_mle_data *sinit_mle =
+ txt_start(__va(txt_read(TXTCR_HEAP_BASE)), TXT_SINIT2MLE);
+ uint32_t *wakeup_addr = __va(sinit_mle->rlp_wakeup_addr);
+
+ join[0] = trampoline_gdt[0] >> 32; /* GDT limit */
+ join[1] = bootsym_phys(trampoline_gdt); /* GDT base */
+ join[2] = (trampoline_gdt_txt - trampoline_gdt) * 8; /* CS selector */
+ /* DS = CS + 8 */
+ join[3] = bootsym_phys(txt_ap_entry); /* EIP */
+
+ txt_write(TXTCR_MLE_JOIN, __pa(join));
+ *wakeup_addr = 1;
+ }
+

+ return 0;
+}
+

static int wakeup_secondary_cpu(int phys_apicid, unsigned long start_eip)
{
unsigned long send_status = 0, accept_status = 0;
@@ -439,6 +498,9 @@ static int wakeup_secondary_cpu(int phys_apicid, unsigned long start_eip)
if ( tboot_in_measured_env() && !tboot_wake_ap(phys_apicid, start_eip) )
return 0;

+ if ( ap_boot_method == AP_BOOT_TXT )
+ return wake_ap_in_txt(phys_apicid);
+
/*
* Be paranoid about clearing APIC errors.
*/
@@ -1165,6 +1227,13 @@ static struct notifier_block cpu_smpboot_nfb = {

void __init smp_prepare_cpus(void)
{
+ /*
+ * If the platform is performing a Secure Launch via TXT, secondary
+ * CPUs (APs) will need to be woken up in a TXT-specific way.
+ */
+ if ( slaunch_active && boot_cpu_data.x86_vendor == X86_VENDOR_INTEL )
+ ap_boot_method = AP_BOOT_TXT;
+
register_cpu_notifier(&cpu_smpboot_nfb);

mtrr_aps_sync_begin();
@@ -1454,6 +1523,12 @@ void __init smp_cpus_done(void)

mtrr_save_state();
mtrr_aps_sync_end();
+
+ /*
+ * After the initial startup the DRTM-specific method for booting APs
+ * should no longer be used unless DRTM sequence is started again.
+ */
+ ap_boot_method = AP_BOOT_NORMAL;
}

void __init smp_intr_init(void)
diff --git a/xen/arch/x86/x86_64/asm-offsets.c b/xen/arch/x86/x86_64/asm-offsets.c
index f0aaf0f4ba..94f2995fff 100644
--- a/xen/arch/x86/x86_64/asm-offsets.c
+++ b/xen/arch/x86/x86_64/asm-offsets.c
@@ -246,4 +246,7 @@ void __dummy__(void)
DEFINE(SL_EIR_size, sizeof(struct slaunch_early_init_results));
BLANK();
#endif
+
+ DEFINE(ASM_AP_BOOT_TXT, AP_BOOT_TXT);
+ BLANK();
}
--
2.55.0

[Sergii Dmytruk]

Go through entires in the DRTM policy of SLRT to hash and extend data
that they describe into corresponding PCRs.

Addresses are being zeroed on measuring platform-specific data to
prevent measurements from changing when the only thing that has changed
is an address. Addresses can vary due to bootloader, firmware or user
doing something differently or just if GRUB gets bigger in size due to
inclusion of more modules and ends up offsetting newly allocated memory.

Signed-off-by: Krystian Hebel <krystia...@3mdeb.com>
Signed-off-by: Sergii Dmytruk <sergii....@3mdeb.com>

---

Notes:
v4: use SLR_TABLE_REVISION in slaunch_measure_slrt()
v4: don't cast away const of slr_next_entry_by_tag()
v4: use container_of()
v4: take changes of `struct boot_module` into account

xen/arch/x86/include/asm/slaunch.h | 14 ++
xen/arch/x86/setup.c | 15 ++
xen/arch/x86/slaunch.c | 217 +++++++++++++++++++++++++++++
3 files changed, 246 insertions(+)

diff --git a/xen/arch/x86/include/asm/slaunch.h b/xen/arch/x86/include/asm/slaunch.h
index 65aab01f04..1b2c5957e4 100644
--- a/xen/arch/x86/include/asm/slaunch.h
+++ b/xen/arch/x86/include/asm/slaunch.h
@@ -31,6 +31,8 @@
#define DLE_EVTYPE_SLAUNCH_START (DLE_EVTYPE_BASE + 0x103)
#define DLE_EVTYPE_SLAUNCH_END (DLE_EVTYPE_BASE + 0x104)

+struct boot_info;

+
struct slaunch_early_init_results
{
uint32_t mbi_pa;

@@ -67,6 +69,18 @@ void slaunch_map_mem_regions(void);
/* Marks regions of memory as used to avoid their corruption. */
void slaunch_reserve_mem_regions(void);

+/* Measures essential parts of SLR table before making use of them. */
+void slaunch_measure_slrt(void);
+
+/*
+ * Takes measurements of DRTM policy entries except for MBI and SLRT which
+ * should have been measured by the time this is called. Also performs sanity
+ * checks of the policy and panics on failure. In particular, the function
+ * verifies that DRTM is consistent with modules obtained from MultibootInfo
+ * (MBI) and written to struct boot_info in setup.c.
+ */
+void slaunch_process_drtm_policy(const struct boot_info *bi);
+
/*

* This helper function is used to map memory below 4 GiB using L2 page tables

* by aligning mapped regions to 2MB. This way page allocator (which at this

diff --git a/xen/arch/x86/setup.c b/xen/arch/x86/setup.c
index fbc44b0174..fd712d69e3 100644
--- a/xen/arch/x86/setup.c
+++ b/xen/arch/x86/setup.c
@@ -1473,6 +1473,13 @@ void asmlinkage __init noreturn __start_xen(void)
if ( slaunch_active )
{
slaunch_map_mem_regions();
+
+ /*
+ * SLRT needs to be measured here because it is used by init_e820(), the
+ * rest is measured slightly below by slaunch_process_drtm_policy().
+ */
+ slaunch_measure_slrt();
+
slaunch_reserve_mem_regions();
}

@@ -1494,6 +1501,14 @@ void asmlinkage __init noreturn __start_xen(void)
/* Create a temporary copy of the E820 map. */
memcpy(&boot_e820, &e820, sizeof(e820));

+ /*
+ * Process all yet unmeasured DRTM entries after E820 initialization to not
+ * do this while memory is uncached (too slow). This must also happen before
+ * modules are relocated or used.
+ */
+ if ( slaunch_active )
+ slaunch_process_drtm_policy(bi);
+
/* Early kexec reservation (explicit static start address). */
nr_pages = 0;
for ( i = 0; i < e820.nr_map; i++ )
diff --git a/xen/arch/x86/slaunch.c b/xen/arch/x86/slaunch.c
index 83dce3d57d..ac62301f93 100644
--- a/xen/arch/x86/slaunch.c
+++ b/xen/arch/x86/slaunch.c
@@ -7,14 +7,17 @@

#include <xen/compiler.h>
#include <xen/init.h>
+#include <xen/kernel.h>
#include <xen/macros.h>
#include <xen/mm.h>
#include <xen/sections.h>
#include <xen/types.h>

+#include <asm/bootinfo.h>
#include <asm/e820.h>
#include <asm/intel-txt.h>
#include <asm/page.h>
+#include <asm/processor.h>

#include <asm/setup.h>
#include <asm/slaunch.h>
#include <asm/slaunch-tpm.h>

@@ -114,6 +117,220 @@ void __init slaunch_reserve_mem_regions(void)
}
}

+void __init slaunch_measure_slrt(void)
+{
+ struct slr_table *slrt = slaunch_get_slrt();
+
+ if ( slrt->revision == SLR_TABLE_REVISION )

+ {
+ const struct slr_entry_hdr *entry;

+
+ /*
+ * In revision one of the SLRT, only platform-specific info table is
+ * measured.
+ */
+ struct slr_entry_intel_info tmp;

+
+ entry = slr_next_entry_by_tag(slrt, NULL, SLR_ENTRY_INTEL_INFO);

+ if ( entry == NULL )
+ panic("SLRT is missing Intel-specific information!\n");
+
+ tmp = *container_of(entry, const struct slr_entry_intel_info, hdr);
+ tmp.boot_params_base = 0;
+ tmp.txt_heap = 0;
+
+ slaunch_hash_extend(DRTM_LOC, DRTM_DATA_PCR, (uint8_t *)&tmp,
+ sizeof(tmp), DLE_EVTYPE_SLAUNCH, NULL, 0);
+ }
+ else
+ {
+ /*
+ * slaunch_get_slrt() checks that the revision is valid, so we must not
+ * get here unless the code is wrong.
+ */
+ panic("Unhandled SLRT revision: %d!\n", slrt->revision);
+ }
+}
+
+static const struct slr_entry_policy *__init
+slr_get_policy(const struct slr_table *slrt)

+{
+ const struct slr_entry_hdr *entry;

+ const struct slr_entry_policy *policy;
+
+ entry = slr_next_entry_by_tag(slrt, NULL, SLR_ENTRY_DRTM_POLICY);
+ if (entry == NULL)
+ panic("SLRT is missing DRTM policy!\n");
+
+ policy = container_of(entry, const struct slr_entry_policy, hdr);
+

+ /* XXX: are newer revisions allowed? */

+ if ( policy->revision != SLR_POLICY_REVISION )
+ panic("DRTM policy in SLRT is of unsupported revision: %#04x!\n",
+ slrt->revision);
+
+ return policy;
+}
+
+static void __init
+check_slrt_policy_entry(struct slr_policy_entry *policy_entry,
+ int idx,
+ const struct slr_table *slrt)
+{
+ if ( policy_entry->entity_type != SLR_ET_SLRT )
+ panic("Expected DRTM policy entry #%d to describe SLRT, got %#04x!\n",
+ idx, policy_entry->entity_type);
+ if ( policy_entry->pcr != DRTM_DATA_PCR )
+ panic("SLRT was measured to PCR-%d instead of PCR-%d!\n", DRTM_DATA_PCR,
+ policy_entry->pcr);
+ if ( policy_entry->entity != (uint64_t)__pa(slrt) )
+ panic("SLRT address (%#08lx) differs from its DRTM entry (%#08lx)\n",
+ __pa(slrt), policy_entry->entity);
+}
+
+/* Returns number of policy entries that were already measured. */
+static unsigned int __init
+check_drtm_policy(const struct slr_table *slrt,
+ const struct slr_entry_policy *policy,
+ struct slr_policy_entry *policy_entry,
+ const struct boot_info *bi)
+{
+ uint32_t i;
+ uint32_t num_mod_entries;
+
+ if ( policy->nr_entries < 2 )
+ panic("DRTM policy in SLRT contains less than 2 entries (%d)!\n",
+ policy->nr_entries);
+
+ /*
+ * MBI policy entry must be the first one, so that measuring order matches
+ * policy order.
+ */
+ if ( policy_entry[0].entity_type != SLR_ET_MULTIBOOT2_INFO )
+ panic("First entry of DRTM policy in SLRT is not MBI: %#04x!\n",
+ policy_entry[0].entity_type);
+ if ( policy_entry[0].pcr != DRTM_DATA_PCR )
+ panic("MBI was measured to %d instead of %d PCR!\n", DRTM_DATA_PCR,
+ policy_entry[0].pcr);
+
+ /* SLRT policy entry must be the second one. */
+ check_slrt_policy_entry(&policy_entry[1], 1, slrt);
+
+ for ( i = 0; i < bi->nr_modules; i++ )
+ {
+ uint16_t j;
+ const struct boot_module *mod = &bi->mods[i];
+
+ if (mod->arch.relocated || mod->arch.released)
+ {
+ panic("Multiboot module \"%s\" (at %d) was consumed before measurement\n",
+ (const char *)__va(mod->arch.cmdline_pa), i);
+ }
+
+ for ( j = 2; j < policy->nr_entries; j++ )
+ {
+ if ( policy_entry[j].entity_type != SLR_ET_MULTIBOOT2_MODULE )
+ continue;
+
+ if ( policy_entry[j].entity == mod->start &&
+ policy_entry[j].size == mod->size )
+ break;
+ }
+
+ if ( j >= policy->nr_entries )
+ {
+ panic("Couldn't find Multiboot module \"%s\" (at %d) in DRTM of Secure Launch\n",
+ (const char *)__va(mod->arch.cmdline_pa), i);
+ }
+ }
+
+ num_mod_entries = 0;
+ for ( i = 0; i < policy->nr_entries; i++ )
+ {
+ if ( policy_entry[i].entity_type == SLR_ET_MULTIBOOT2_MODULE )
+ num_mod_entries++;
+ }
+
+ if ( bi->nr_modules != num_mod_entries )
+ {
+ panic("Unexpected number of Multiboot modules: %d instead of %d\n",
+ (int)bi->nr_modules, (int)num_mod_entries);
+ }
+
+ /*
+ * MBI was measured in slaunch_measure_mbi().
+ * SLRT was measured in slaunch_measure_slrt().
+ */
+ return 2;
+}
+
+void __init slaunch_process_drtm_policy(const struct boot_info *bi)
+{
+ const struct slr_table *slrt;
+ const struct slr_entry_policy *policy;
+ struct slr_policy_entry *policy_entry;
+ uint16_t i;
+ unsigned int measured;
+
+ slrt = slaunch_get_slrt();
+
+ policy = slr_get_policy(slrt);
+ policy_entry = (void *)policy + sizeof(*policy);
+
+ measured = check_drtm_policy(slrt, policy, policy_entry, bi);
+ for ( i = 0; i < measured; i++ )
+ policy_entry[i].flags |= SLR_POLICY_FLAG_MEASURED;
+
+ for ( i = measured; i < policy->nr_entries; i++ )
+ {
+ int rc;
+ uint64_t start = policy_entry[i].entity;
+ uint64_t size = policy_entry[i].size;
+
+ /* No already measured entries are expected here. */
+ if ( policy_entry[i].flags & SLR_POLICY_FLAG_MEASURED )
+ panic("DRTM entry at %d was measured out of order!\n", i);
+
+ switch ( policy_entry[i].entity_type )
+ {
+ case SLR_ET_MULTIBOOT2_INFO:
+ panic("Duplicated MBI entry in DRTM of Secure Launch at %d\n", i);
+ case SLR_ET_SLRT:
+ panic("Duplicated SLRT entry in DRTM of Secure Launch at %d\n", i);
+
+ case SLR_ET_UNSPECIFIED:
+ case SLR_ET_BOOT_PARAMS:
+ case SLR_ET_SETUP_DATA:
+ case SLR_ET_CMDLINE:
+ case SLR_ET_UEFI_MEMMAP:
+ case SLR_ET_RAMDISK:
+ case SLR_ET_MULTIBOOT2_MODULE:
+ case SLR_ET_TXT_OS2MLE:
+ /* Measure this entry below. */
+ break;
+
+ case SLR_ET_UNUSED:
+ /* Skip this entry. */
+ continue;
+ }
+
+ if ( policy_entry[i].flags & SLR_POLICY_IMPLICIT_SIZE )
+ panic("Unexpected implicitly-sized DRTM entry of Secure Launch at %d (type %d, info: %s)\n",
+ i, policy_entry[i].entity_type, policy_entry[i].evt_info);
+
+ rc = slaunch_map_l2(start, size);

+ BUG_ON(rc != 0);
+

+ slaunch_hash_extend(DRTM_LOC, policy_entry[i].pcr, __va(start), size,
+ DLE_EVTYPE_SLAUNCH,
+ (uint8_t *)policy_entry[i].evt_info,
+ strnlen(policy_entry[i].evt_info,
+ TPM_EVENT_INFO_LENGTH));
+
+ policy_entry[i].flags |= SLR_POLICY_FLAG_MEASURED;
+ }
+}
+

int __init slaunch_map_l2(paddr_t paddr, size_t size)

{

unsigned long aligned_paddr = paddr & ~((1ULL << L2_PAGETABLE_SHIFT) - 1);

--
2.55.0

[Sergii Dmytruk]

Secure Launch won't initiate DRTM on S3 resume (the code for starting
DRTM is not part of Xen), so abort a request to perform S3 suspend to
not lose the state of DRTM PCRs.

Signed-off-by: Sergii Dmytruk <sergii....@3mdeb.com>
---

Notes:

v4: return EACCES instead of EPERM

xen/arch/x86/acpi/power.c | 8 ++++++++
1 file changed, 8 insertions(+)

diff --git a/xen/arch/x86/acpi/power.c b/xen/arch/x86/acpi/power.c
index 3452650a61..8428766f82 100644
--- a/xen/arch/x86/acpi/power.c
+++ b/xen/arch/x86/acpi/power.c
@@ -30,6 +30,7 @@
#include <asm/microcode.h>
#include <asm/mwait.h>
#include <asm/prot-key.h>
+#include <asm/slaunch.h>
#include <asm/spec_ctrl.h>
#include <asm/tboot.h>
#include <asm/trampoline.h>
@@ -335,6 +336,13 @@ int acpi_enter_sleep(const struct xenpf_enter_acpi_sleep *sleep)
PAGE_SIZE - acpi_sinfo.vector_width / 8)) )
return -EOPNOTSUPP;

+ /* Secure Launch won't initiate DRTM on S3 resume, so abort S3 suspend. */
+ if ( sleep->sleep_state == ACPI_STATE_S3 && slaunch_active )
+ {
+ printk(XENLOG_INFO "SLAUNCH: refusing switching into ACPI S3 state.\n");
+ return -EACCES;
+ }
+
if ( sleep->flags & XENPF_ACPI_SLEEP_EXTENDED )
{
if ( !acpi_sinfo.sleep_control.address ||
--
2.55.0

[Sergii Dmytruk]

Handle the state after secure-kernel-loader (SKL) in boot/head.S.

Use slr_entry_amd_info::boot_params_base on AMD with SKINIT to get MBI
location.

Locate SLRT which is bootloader's data after SKL on AMD.

Measure AMD-specific data in slaunch_measure_slrt().

Find Intel-compatible TPM event log structure within vendor data of
TCG-compliant event logs.

Signed-off-by: Krystian Hebel <krystia...@3mdeb.com>

Signed-off-by: Sergii Dmytruk <sergii....@3mdeb.com>
---

Notes:

v4: squashed "x86/slaunch: support AMD SKINIT" and "x86/boot/slaunch-early: find MBI and SLRT on AMD"
v4: use CONFIG_SLAUNCH
v4: update large comment in head.S
v4: define slaunch_is_amd_drtm() in a header and use twice to avoid duplication
v4: %#04x => %#x in panic("SLRT is for unexpected architecture ...")
v4: use container_of()
v4: don't drop `const` from the result of `slr_next_entry_by_tag()`

xen/arch/x86/boot/head.S | 42 ++++++++++++---
xen/arch/x86/boot/slaunch-early.c | 52 ++++++++++++++++++
xen/arch/x86/e820.c | 2 +-
xen/arch/x86/include/asm/slaunch.h | 30 +++++++++++
xen/arch/x86/include/asm/tpm1.h | 15 ++++++
xen/arch/x86/slaunch-tpm.c | 26 +++++++++
xen/arch/x86/slaunch.c | 87 ++++++++++++++++++++++++------
7 files changed, 231 insertions(+), 23 deletions(-)

diff --git a/xen/arch/x86/boot/head.S b/xen/arch/x86/boot/head.S
index ff46579904..bf38aef21c 100644
--- a/xen/arch/x86/boot/head.S
+++ b/xen/arch/x86/boot/head.S
@@ -358,10 +358,14 @@ cs32_switch:

#if CONFIG_SLAUNCH
/*
- * Entry point for TrenchBoot Secure Launch on Intel TXT platforms.
+ * Entry point for TrenchBoot Secure Launch, common for Intel TXT and
+ * AMD Secure Startup, but state is slightly different.
+ *
+ * On Intel
+ * --------
*

* CPU is in 32b protected mode with paging disabled. On entry:

- * - %ebx = %eip = MLE entry point,
+ * - %ebx = %eip = this entry point,

* - stack pointer is undefined,

* - CS is flat 4GB code segment,

* - DS, ES, SS, FS and GS are undefined according to TXT SDG, but this

@@ -382,13 +386,36 @@ cs32_switch:

* writing a non-zero value at a MONITORed address or via

* GETSEC[WAKEUP] instruction, depending on which is supported by a

* given SINIT ACM
+ *

+ * On AMD (as implemented by TrenchBoot's secure-kernel-loader or SKL)
+ * -------------------------------------------------------------------

+ *
+ * CPU is in 32b protected mode with paging disabled. On entry:

+ * - %ebx = %eip = this entry point,
+ * - %ebp holds base address of SKL
+ * - stack pointer is treated as undefined for parity with TXT,

+ * - CS is flat 4GB code segment,

+ * - DS, ES, SS are flat 4GB data segments, but treated as undefined for
+ * parity with TXT.

+ *
+ * Additional restrictions:

+ * - interrupts (including NMIs and SMIs) are disabled and must be
+ * enabled later

+ * - APs must be brought up by SIPI without an INIT
*/
slaunch_stub_entry:

/* Calculate the load base address. */

mov %ebx, %esi
sub $sym_offs(slaunch_stub_entry), %esi

- /* Mark Secure Launch boot protocol and jump to common entry. */
+ /* On AMD, %ebp holds the base address of SLB, save it for later. */
+ mov %ebp, %ebx
+
+ /*
+ * Mark Secure Launch boot protocol and jump to common entry. Note that
+ * all general purpose registers except %ebx and %esi are clobbered
+ * between here and .Lslaunch_proto.
+ */
mov $SLAUNCH_BOOTLOADER_MAGIC, %eax
jmp .Lset_stack
#endif /* CONFIG_SLAUNCH */
@@ -524,15 +551,18 @@ __start:
sub $SL_EIR_size, %esp

push %esp /* pointer to output structure */

+ push %ebx /* Slaunch parameter on AMD */

mov $sym_offs(__2M_rwdata_end), %ecx /* end of target image */

mov $sym_offs(_start), %edx /* target base address */

mov %esi, %eax /* load base address */

/*
- * slaunch_early_init(load/eax, tgt/edx, tgt_end/ecx, ret/stk) using
- * fastcall calling convention.
+ * slaunch_early_init(load/eax, tgt/edx, tgt_end/ecx,
+ * slaunch/stk, ret/stk)
+ *
+ * Uses fastcall calling convention.
*/
call slaunch_early_init
- add $4, %esp /* pop the fourth parameter */
+ add $8, %esp /* pop last two parameters */

/* Move outputs of slaunch_early_init() from the stack. */

pop %ebx /* store physical MBI address in EBX where

diff --git a/xen/arch/x86/boot/slaunch-early.c b/xen/arch/x86/boot/slaunch-early.c
index 00c772cfdf..9b16602ac8 100644
--- a/xen/arch/x86/boot/slaunch-early.c
+++ b/xen/arch/x86/boot/slaunch-early.c
@@ -13,9 +13,23 @@
#include <asm/intel-txt.h>
#include <asm/slaunch.h>

+/*
+ * The AMD-defined structure layout for the SLB. The last two fields are
+ * SL-specific.
+ */
+struct skinit_sl_header
+{
+ uint16_t skl_entry_point;
+ uint16_t length;
+ uint8_t reserved[62];
+ uint16_t skl_info_offset;
+ uint16_t bootloader_data_offset;
+} __packed;
+
void asmlinkage slaunch_early_init(uint32_t load_base_addr,
uint32_t tgt_base_addr,
uint32_t tgt_end_addr,
+ uint32_t slaunch_param,
struct slaunch_early_init_results *result)
{
void *txt_heap;
@@ -26,6 +40,44 @@ void asmlinkage slaunch_early_init(uint32_t load_base_addr,
const struct slr_entry_intel_info *intel_info;

uint32_t size = tgt_end_addr - tgt_base_addr;

+ if ( slaunch_is_amd_drtm() )
+ {
+ /*
+ * Not an Intel CPU. Currently the only other option is AMD with SKINIT
+ * and secure-kernel-loader (SKL).
+ */
+ const struct slr_entry_amd_info *amd_info;
+ const struct skinit_sl_header *sl_header = (void *)slaunch_param;
+
+ /*
+ * slaunch_param holds a physical address of SLB.
+ * Bootloader's data is SLRT.
+ */
+ result->slrt_pa = slaunch_param + sl_header->bootloader_data_offset;
+
+ slrt = (struct slr_table *)(uintptr_t)result->slrt_pa;
+
+ entry = slr_next_entry_by_tag(slrt, NULL, SLR_ENTRY_AMD_INFO);

+ if ( entry == NULL )

+ {
+ /* No reset mechanism or an error register on AMD. */
+ asm volatile ("ud2");
+ unreachable();
+ }
+
+ amd_info = container_of(entry, const struct slr_entry_amd_info, hdr);
+ /* Basic checks only, SKL checked and consumed the rest. */
+ if ( amd_info->hdr.size != sizeof(*amd_info) )
+ {
+ /* No reset mechanism or an error register on AMD. */
+ asm volatile ("ud2");
+ unreachable();
+ }
+
+ result->mbi_pa = amd_info->boot_params_base;
+ return;
+ }
+

txt_heap = txt_init();
os_mle = txt_start(txt_heap, TXT_OS2MLE);

os_sinit = txt_start(txt_heap, TXT_OS2SINIT);
diff --git a/xen/arch/x86/e820.c b/xen/arch/x86/e820.c
index c63b0b12cc..964a02384d 100644
--- a/xen/arch/x86/e820.c
+++ b/xen/arch/x86/e820.c
@@ -501,7 +501,7 @@ static void __init machine_specific_memory_setup(struct e820map *raw)

uint64_t top_of_ram, size;
unsigned int i;

- if ( slaunch_active )

+ if ( slaunch_active && boot_cpu_data.x86_vendor == X86_VENDOR_INTEL )

txt_restore_mtrrs(e820_verbose);

sanitize_e820_map(raw->map, &raw->nr_map);
diff --git a/xen/arch/x86/include/asm/slaunch.h b/xen/arch/x86/include/asm/slaunch.h
index 1b2c5957e4..a9c009fa96 100644
--- a/xen/arch/x86/include/asm/slaunch.h
+++ b/xen/arch/x86/include/asm/slaunch.h
@@ -17,6 +17,8 @@
#include <xen/slr-table.h>
#include <xen/types.h>

+#include <asm/x86-vendors.h>
+
#define DRTM_LOC 2
#define DRTM_CODE_PCR 17
#define DRTM_DATA_PCR 18
@@ -56,6 +58,34 @@ static bool slaunch_active = false;
*/
extern uint32_t slaunch_slrt;

+#ifdef __EARLY_SLAUNCH__
+
+static inline bool slaunch_is_amd_drtm(void)
+{
+ /*
+ * asm/processor.h can't be included in early code, which means neither
+ * cpuid() function nor boot_cpu_data can be used here.
+ */
+ uint32_t eax, ebx, ecx, edx;
+ asm volatile ( "cpuid"
+ : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)
+ : "0" (0), "c" (0) );
+ return ebx == X86_VENDOR_AMD_EBX
+ && ecx == X86_VENDOR_AMD_ECX
+ && edx == X86_VENDOR_AMD_EDX;
+}
+
+#else /* __EARLY_SLAUNCH__ */
+
+#include <asm/cpufeature.h>
+
+static inline bool slaunch_is_amd_drtm(void)
+{
+ return boot_cpu_data.x86_vendor == X86_VENDOR_AMD;

+}
+
+#endif /* __EARLY_SLAUNCH__ */
+

/*

* Retrieves pointer to SLRT. Checks table's validity and maps it as necessary.

*/
diff --git a/xen/arch/x86/include/asm/tpm1.h b/xen/arch/x86/include/asm/tpm1.h

index d1cb2cc041..57a60223ba 100644
--- a/xen/arch/x86/include/asm/tpm1.h
+++ b/xen/arch/x86/include/asm/tpm1.h
@@ -76,4 +76,19 @@ struct TPM12_PCREvent {
uint8_t Data[];
};

+struct tpm1_spec_id_event {

+ uint32_t pcrIndex;
+ uint32_t eventType;
+ uint8_t digest[20];
+ uint32_t eventSize;
+ uint8_t signature[16];
+ uint32_t platformClass;
+ uint8_t specVersionMinor;
+ uint8_t specVersionMajor;
+ uint8_t specErrata;
+ uint8_t uintnSize;

+ uint8_t vendorInfoSize;
+ uint8_t vendorInfo[0]; /* variable number of members */
+} __packed;
+
#endif /* X86_TPM1_H */
diff --git a/xen/arch/x86/slaunch-tpm.c b/xen/arch/x86/slaunch-tpm.c
index e3b7341cc5..2f8e598706 100644
--- a/xen/arch/x86/slaunch-tpm.c
+++ b/xen/arch/x86/slaunch-tpm.c
@@ -79,6 +79,16 @@ create_log_event12(struct txt_ev_log_container_12 *evt_log,
if (evt_log == NULL)
return log_hashes;

+ if ( slaunch_is_amd_drtm() )
+ {
+ /*
+ * On AMD, TXT-compatible structure is stored as vendor data of
+ * TCG-defined event log header.
+ */
+ struct tpm1_spec_id_event *spec_id = (void *)evt_log;
+ evt_log = (struct txt_ev_log_container_12 *)&spec_id->vendorInfo[0];

+ }
+
new_entry = (void *)evt_log + evt_log->NextEventOffset;

/*
@@ -114,6 +124,22 @@ find_evt_log_ext_data(struct tpm2_spec_id_event *evt_log)
struct txt_os_sinit_data *os_sinit;
struct txt_ext_data_element *ext_data;

+ if ( slaunch_is_amd_drtm() )
+ {
+ /*
+ * Event log pointer is defined by TXT specification, but
+ * secure-kernel-loader provides a compatible structure in vendor data
+ * of the log.
+ */
+ uint8_t *data_size =
+ (uint8_t *)&evt_log->digestSizes[evt_log->digestCount];
+ if ( *data_size != sizeof(struct heap_event_log_pointer_element2_1) )
+ return NULL;
+
+ /* Vendor data directly follows a single-byte size. */
+ return (struct heap_event_log_pointer_element2_1 *)(data_size + 1);

+ }
+
os_sinit = txt_start(__va(txt_read(TXTCR_HEAP_BASE)), TXT_OS2SINIT);

ext_data = txt_find_ext_data_element(os_sinit,
TXT_HEAP_EXTDATA_TYPE_EVENT_LOG_POINTER2_1);
diff --git a/xen/arch/x86/slaunch.c b/xen/arch/x86/slaunch.c
index ac62301f93..af88ca9caa 100644
--- a/xen/arch/x86/slaunch.c
+++ b/xen/arch/x86/slaunch.c
@@ -23,6 +23,10 @@
#include <asm/slaunch-tpm.h>
#include <asm/tpm.h>

+/* SLB is 64k, 64k-aligned */
+#define SKINIT_SLB_SIZE 0x10000
+#define SKINIT_SLB_ALIGN 0x10000
+

/*
* These variables are assigned to by the code near Xen's entry point.

*
@@ -48,6 +52,8 @@ struct slr_table *__init slaunch_get_slrt(void)

if ( slrt == NULL )

{
int rc;
+ bool intel_cpu = (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL);
+ uint16_t slrt_architecture = intel_cpu ? SLR_INTEL_TXT : SLR_AMD_SKINIT;

slrt = __va(slaunch_slrt);

@@ -59,9 +65,9 @@ struct slr_table *__init slaunch_get_slrt(void)

/* XXX: are newer revisions allowed? */

if ( slrt->revision != SLR_TABLE_REVISION )

panic("SLRT is of unsupported revision: %#x!\n", slrt->revision);

- if ( slrt->architecture != SLR_INTEL_TXT )
- panic("SLRT is for unexpected architecture: %#x!\n",
- slrt->architecture);
+ if ( slrt->architecture != slrt_architecture )
+ panic("SLRT is for unexpected architecture: %#x != %#x!\n",
+ slrt->architecture, slrt_architecture);

if ( slrt->size > slrt->max_size )

panic("SLRT is larger than its max size: %#x > %#x!\n",

slrt->size, slrt->max_size);
@@ -76,6 +82,23 @@ struct slr_table *__init slaunch_get_slrt(void)
return slrt;
}

+static uint32_t __init get_slb_start(void)
+{
+ /*
+ * The runtime computation relies on size being a power of 2 and equal to
+ * alignment. Make sure these assumptions hold.
+ */
+ BUILD_BUG_ON(SKINIT_SLB_SIZE != SKINIT_SLB_ALIGN);
+ BUILD_BUG_ON(SKINIT_SLB_SIZE == 0);
+ BUILD_BUG_ON((SKINIT_SLB_SIZE & (SKINIT_SLB_SIZE - 1)) != 0);
+
+ /*
+ * Rounding any address within SLB down to alignment gives SLB base and
+ * SLRT is inside SLB on AMD.
+ */
+ return slaunch_slrt & ~(SKINIT_SLB_SIZE - 1);
+}
+
void __init slaunch_map_mem_regions(void)
{
int rc;
@@ -86,7 +109,10 @@ void __init slaunch_map_mem_regions(void)
BUG_ON(rc != 0);

/* Vendor-specific part. */
- txt_map_mem_regions();
+ if ( boot_cpu_data.x86_vendor == X86_VENDOR_INTEL )
+ txt_map_mem_regions();
+ else if ( boot_cpu_data.x86_vendor == X86_VENDOR_AMD )
+ slaunch_map_l2(get_slb_start(), SKINIT_SLB_SIZE);

slaunch_find_log(slaunch_get_slrt(), &evt_log_addr, &evt_log_size);

if ( evt_log_addr != 0 )

@@ -98,17 +124,27 @@ void __init slaunch_map_mem_regions(void)

void __init slaunch_reserve_mem_regions(void)
{
+ int ok;
paddr_t evt_log_addr;
uint32_t evt_log_size;

/* Vendor-specific part. */
- txt_reserve_mem_regions();
+ if ( boot_cpu_data.x86_vendor == X86_VENDOR_INTEL )
+ {
+ txt_reserve_mem_regions();
+ }
+ else if ( boot_cpu_data.x86_vendor == X86_VENDOR_AMD )
+ {
+ uint64_t slb_start = get_slb_start();
+ uint64_t slb_end = slb_start + SKINIT_SLB_SIZE;
+ printk("SLAUNCH: reserving SLB [%#lx, %#lx)\n", slb_start, slb_end);
+ ok = reserve_e820_ram(&e820_raw, slb_start, slb_end);
+ BUG_ON(!ok);
+ }

slaunch_find_log(slaunch_get_slrt(), &evt_log_addr, &evt_log_size);

if ( evt_log_addr != 0 )

{
- int ok;
-

printk("SLAUNCH: reserving event log [%#lx, %#lx)\n", evt_log_addr,

evt_log_addr + evt_log_size);
ok = reserve_e820_ram(&e820_raw, evt_log_addr,
@@ -129,18 +165,37 @@ void __init slaunch_measure_slrt(void)

* In revision one of the SLRT, only platform-specific info table is

* measured.
*/
- struct slr_entry_intel_info tmp;
+ if ( boot_cpu_data.x86_vendor == X86_VENDOR_INTEL )
+ {
+ struct slr_entry_intel_info tmp;

- entry = slr_next_entry_by_tag(slrt, NULL, SLR_ENTRY_INTEL_INFO);
- if ( entry == NULL )
- panic("SLRT is missing Intel-specific information!\n");

+ entry = slr_next_entry_by_tag(slrt, NULL, SLR_ENTRY_INTEL_INFO);
+ if ( entry == NULL )
+ panic("SLRT is missing Intel-specific information!\n");

- tmp = *container_of(entry, const struct slr_entry_intel_info, hdr);
- tmp.boot_params_base = 0;
- tmp.txt_heap = 0;

+ tmp = *container_of(entry, const struct slr_entry_intel_info, hdr);
+ tmp.boot_params_base = 0;
+ tmp.txt_heap = 0;

- slaunch_hash_extend(DRTM_LOC, DRTM_DATA_PCR, (uint8_t *)&tmp,
- sizeof(tmp), DLE_EVTYPE_SLAUNCH, NULL, 0);

+ slaunch_hash_extend(DRTM_LOC, DRTM_DATA_PCR, (uint8_t *)&tmp,
+ sizeof(tmp), DLE_EVTYPE_SLAUNCH, NULL, 0);
+ }

+ else if ( boot_cpu_data.x86_vendor == X86_VENDOR_AMD )
+ {
+ struct slr_entry_amd_info tmp;
+
+ entry = slr_next_entry_by_tag(slrt, NULL, SLR_ENTRY_AMD_INFO);

+ if ( entry == NULL )

+ panic("SLRT is missing AMD-specific information!\n");
+
+ tmp = *container_of(entry, const struct slr_entry_amd_info, hdr);
+ tmp.next = 0;
+ tmp.slrt_base = 0;

+ tmp.boot_params_base = 0;
+

+ slaunch_hash_extend(DRTM_LOC, DRTM_DATA_PCR, (uint8_t *)&tmp,
+ sizeof(tmp), DLE_EVTYPE_SLAUNCH, NULL, 0);
+ }
}

else
{
--
2.55.0

[Sergii Dmytruk]

When running on an EFI-enabled system, Xen needs to have access to Boot
Services in order to initialize itself properly and reach a state in
which a dom0 kernel can operate without issues.

This means that DRTM must be started in the middle of Xen's
initialization process. This effect is achieved via a callback into
a TrenchBoot-enabled bootloader (GRUB) which is responsible for
initiating DRTM and continuing Xen's initialization process. The latter
is done by branching in Slaunch entry point on a flag to switch back
into long mode before calling the same function which Xen would execute
as the next step without DRTM.

Signed-off-by: Krystian Hebel <krystia...@3mdeb.com>
Signed-off-by: Sergii Dmytruk <sergii....@3mdeb.com>
---

Notes:

v4: -DXEN_BUILD_EFI => -DXEN_BUILD_EFI=1
v4: use CONFIG_SLAUNCH
v4: use pointers to `const` SLRT and TXT heap data
v4: use container_of()
v4: take updates to `struct boot_module` into account
v4: now UEFI_SLR_TABLE_GUID is defined here in efi/boot.c

.gitignore | 1 +
.../eclair_analysis/ECLAIR/out_of_scope.ecl | 1 +
docs/hypervisor-guide/x86/how-xen-boots.rst | 14 +-
xen/arch/x86/Makefile | 12 +-
xen/arch/x86/boot/head.S | 124 +++++++++++++++++
xen/arch/x86/boot/x86_64.S | 14 +-
xen/arch/x86/efi/efi-boot.h | 94 ++++++++++++-
xen/arch/x86/efi/fixmlehdr.c | 127 ++++++++++++++++++
xen/arch/x86/slaunch.c | 75 ++++++++++-

xen/common/efi/boot.c | 6 +
xen/common/efi/runtime.c | 1 +
xen/include/xen/efi.h | 1 +

12 files changed, 455 insertions(+), 15 deletions(-)
create mode 100644 xen/arch/x86/efi/fixmlehdr.c

diff --git a/.gitignore b/.gitignore
index bfc7bdf043..76bc97d5ea 100644
--- a/.gitignore
+++ b/.gitignore
@@ -177,6 +177,7 @@ xen/.xen.elf32
xen/System.map
xen/arch/x86/efi.lds
xen/arch/x86/efi/check.efi
+xen/arch/x86/efi/fixmlehdr
xen/arch/x86/efi/mkreloc
xen/arch/x86/include/asm/asm-macros.h
xen/arch/*/xen.lds
diff --git a/automation/eclair_analysis/ECLAIR/out_of_scope.ecl b/automation/eclair_analysis/ECLAIR/out_of_scope.ecl
index 9bcec4c69d..a09cf5442c 100644
--- a/automation/eclair_analysis/ECLAIR/out_of_scope.ecl
+++ b/automation/eclair_analysis/ECLAIR/out_of_scope.ecl
@@ -19,6 +19,7 @@

-doc_begin="Build tools are out of scope."
-file_tag+={out_of_scope_tools,"^xen/tools/.*$"}
+-file_tag+={out_of_scope_tools,"^xen/arch/x86/efi/fixmlehdr\\.c$"}
-file_tag+={out_of_scope_tools,"^xen/arch/x86/efi/mkreloc\\.c$"}
-file_tag+={out_of_scope_tools,"^xen/arch/x86/boot/mkelf32\\.c$"}
-doc_end
diff --git a/docs/hypervisor-guide/x86/how-xen-boots.rst b/docs/hypervisor-guide/x86/how-xen-boots.rst
index a841d1e9f8..0b1b62971f 100644
--- a/docs/hypervisor-guide/x86/how-xen-boots.rst
+++ b/docs/hypervisor-guide/x86/how-xen-boots.rst
@@ -56,12 +56,14 @@ which indicates the ability to use the PVH boot protocol, and registers

``__pvh_start`` as the entrypoint, entered in 32bit mode.

A combination of Multiboot 2 and Measured Launched Environment (MLE) headers

-is used to support Dynamic Root of Trust for Measurement (DRTM) for legacy
-(BIOS) boot. DRTM is a way to establish hardware root of trust which
-excludes firmware and is not directly tied to hardware's boot process. The
-separate entry point called ``slaunch_stub_entry`` is used mainly to
-differentiate from other kinds of boots. It moves a magic number to ``EAX``
-before jumping into common startup code. More details about Secure Launch
+is used to support Dynamic Root of Trust for Measurement (DRTM). DRTM is a
+way to establish hardware root of trust which excludes firmware and is not
+directly tied to hardware's boot process. The separate entry point called
+``slaunch_stub_entry`` is used mainly to differentiate from other kinds of
+boots. For a legacy (BIOS) boot, it moves a magic number to ``EAX`` before
+jumping into common startup code. For a EFI boot, it resumes execution of
+Xen.efi which was paused by handing control to a part of a bootloader
+responsible for initiating DRTM sequence. More details about Secure Launch

data structures processed by Xen in this boot mode can be found in

`<https://trenchboot.org/specifications/Secure_Launch/>`_.

diff --git a/xen/arch/x86/Makefile b/xen/arch/x86/Makefile
index 8dbb76a3a0..4f7db9420e 100644
--- a/xen/arch/x86/Makefile
+++ b/xen/arch/x86/Makefile
@@ -89,6 +89,7 @@ extra-y += xen.lds

hostprogs-y += boot/mkelf32
hostprogs-y += efi/mkreloc
+hostprogs-y += efi/fixmlehdr

$(obj)/efi/mkreloc: HOSTCFLAGS += -I$(srctree)/include

@@ -123,6 +124,11 @@ $(TARGET): $(TARGET)-syms $(efi-y) $(obj)/boot/mkelf32

CFLAGS-$(XEN_BUILD_EFI) += -DXEN_BUILD_EFI

+# Expose this build flag as a macro when compiling assembly files.
+ifeq ($(XEN_BUILD_EFI),y)
+XEN_AFLAGS += -DXEN_BUILD_EFI=1
+endif
+
$(TARGET)-syms: $(objtree)/prelink.o $(obj)/xen.lds
$(objtree)/tools/symbols $(all_symbols) --empty > $(dot-target).0.S
$(MAKE) $(build)=$(@D) $(dot-target).0.o
@@ -196,7 +202,7 @@ note_file_option ?= $(note_file)
extra-$(XEN_BUILD_PE) += efi.lds
ifeq ($(XEN_BUILD_PE),y)
$(TARGET).efi: $(obj)/efi/relocs-dummy.o $(obj)/efi/relocs-empty.o $(obj)/efi/mkreloc
-$(TARGET).efi: $(objtree)/prelink.o $(note_file) $(obj)/efi.lds
+$(TARGET).efi: $(objtree)/prelink.o $(note_file) $(obj)/efi.lds $(obj)/efi/fixmlehdr
ifeq ($(CONFIG_DEBUG_INFO),y)
$(if $(filter --strip-debug,$(EFI_LDFLAGS)),echo,:) "Will strip debug info from $(@F)"
endif
@@ -230,6 +236,10 @@ endif
$(LD) $(call EFI_LDFLAGS,$(VIRT_BASE)) -T $(obj)/efi.lds $< $(obj)/efi/relocs-empty.o \
$(dot-target).2r.o $(dot-target).2s.o $(orphan-handling-y) \
$(note_file_option) -o $@
+ifeq ($(CONFIG_SLAUNCH),y)
+ # update entry point's address by taking image offset into account
+ $(obj)/efi/fixmlehdr $@ $(XEN_IMG_OFFSET)
+endif
$(NM) -pa --format=sysv $@ \
| $(objtree)/tools/symbols --all-symbols --xensyms --sysv --sort \
> $@.map
diff --git a/xen/arch/x86/boot/head.S b/xen/arch/x86/boot/head.S
index bf38aef21c..22b331a45c 100644
--- a/xen/arch/x86/boot/head.S
+++ b/xen/arch/x86/boot/head.S
@@ -408,6 +408,12 @@ slaunch_stub_entry:

mov %ebx, %esi
sub $sym_offs(slaunch_stub_entry), %esi

+#if XEN_BUILD_EFI
+ /* If the flag is already set, then Xen should continue execution. */
+ cmpb $0, sym_esi(slaunch_active)
+ jne slaunch_efi_jumpback
+#endif

+
/* On AMD, %ebp holds the base address of SLB, save it for later. */

mov %ebp, %ebx

@@ -855,6 +861,124 @@ trampoline_setup:
/* Jump into the relocated trampoline. */
lret

+#if XEN_BUILD_EFI && CONFIG_SLAUNCH
+
+ /*
+ * The state matches that of slaunch_stub_entry above, but with %esi
+ * already initialized.
+ */
+slaunch_efi_jumpback:
+ lea STACK_SIZE - CPUINFO_sizeof + sym_esi(cpu0_stack), %esp
+
+ /* Prepare gdt and segments. */
+ add %esi, sym_esi(gdt_boot_base)
+ lgdt sym_esi(gdt_boot_descr)
+
+ mov $BOOT_DS, %ecx
+ mov %ecx, %ds
+ mov %ecx, %es
+ mov %ecx, %ss
+
+ push $BOOT_CS32
+ lea sym_esi(.Lgdt_is_set),%edx
+ push %edx
+ lret
+.Lgdt_is_set:
+
+ /*
+ * Stash TSC as above because it was zeroed on jumping into bootloader
+ * to not interfere with measurements.
+ */
+ rdtsc
+ mov %eax, sym_esi(boot_tsc_stamp)
+ mov %edx, 4 + sym_esi(boot_tsc_stamp)
+
+ /*
+ * Clear the pagetables before the use. We are loaded below 4GiB and
+ * this avoids the need for writing to higher dword of each entry.
+ * Additionally, this ensures those dwords are actually zero and the
+ * mappings aren't manipulated from outside.
+ */
+ lea sym_esi(bootmap_start), %edi
+ lea sym_esi(bootmap_end), %ecx
+ sub %edi, %ecx
+ xor %eax, %eax
+ shr $2, %ecx
+ rep stosl
+
+ /* 1x L1 page, 512 entries mapping total of 2M. */
+ lea sym_esi(l1_bootmap), %edi
+ mov $512, %ecx
+ mov $(__PAGE_HYPERVISOR + 512 * PAGE_SIZE), %edx
+.Lfill_l1_identmap:
+ sub $PAGE_SIZE, %edx
+ /* Loop runs for ecx=[512..1] for entries [511..0], hence -8. */
+ mov %edx, -8(%edi,%ecx,8)
+ loop .Lfill_l1_identmap
+
+ /* 4x L2 pages, each page mapping 1G of RAM. */
+ lea sym_esi(l2_bootmap), %edi
+ /* 1st entry points to L1. */
+ lea (sym_offs(l1_bootmap) + __PAGE_HYPERVISOR)(%esi), %edx
+ mov %edx, (%edi)
+ /* Other entries are 2MB pages. */
+ mov $(4 * 512 - 1), %ecx
+ /*
+ * Value below should be 4GB + flags, which wouldn't fit in 32b
+ * register. To avoid warning from the assembler, 4GB is skipped here.
+ * Substitution in first iteration makes the value roll over and point
+ * to 4GB - 2MB + flags.
+ */
+ mov $(_PAGE_PSE + __PAGE_HYPERVISOR), %edx
+.Lfill_l2_identmap:
+ sub $(1 << L2_PAGETABLE_SHIFT), %edx
+ /* Loop runs for ecx=[2047..1] for entries [2047..1]. */
+ mov %edx, (%edi,%ecx,8)
+ loop .Lfill_l2_identmap
+
+ /* 1x L3 page, mapping the 4x L2 pages. */
+ lea sym_esi(l3_bootmap), %edi
+ mov $4, %ecx
+ lea (sym_offs(l2_bootmap) + 4 * PAGE_SIZE + __PAGE_HYPERVISOR)(%esi), %edx
+.Lfill_l3_identmap:
+ sub $PAGE_SIZE, %edx
+ /* Loop runs for ecx=[4..1] for entries [3..0], hence -8. */
+ mov %edx, -8(%edi,%ecx,8)
+ loop .Lfill_l3_identmap
+
+ /* 1x L4 page, mapping the L3 page. */
+ lea (sym_offs(l3_bootmap) + __PAGE_HYPERVISOR)(%esi), %edx
+ mov %edx, sym_esi(l4_bootmap)
+
+ /* Restore CR4, PAE must be enabled before IA-32e mode */
+ mov %cr4, %ecx
+ or $X86_CR4_PAE, %ecx
+ mov %ecx, %cr4
+
+ /* Load PML4 table location into PT base register */
+ lea sym_esi(l4_bootmap), %eax
+ mov %eax, %cr3
+
+ /* Enable IA-32e mode and paging */
+ mov $MSR_EFER, %ecx
+ rdmsr
+ or $EFER_LME >> 8, %ah
+ wrmsr
+
+ mov %cr0, %eax
+ or $X86_CR0_PG | X86_CR0_NE | X86_CR0_TS | X86_CR0_MP, %eax
+ mov %eax, %cr0
+
+ /* Now in IA-32e compatibility mode, use lret to jump to 64b mode */
+ lea sym_esi(start_xen_from_efi), %ecx
+ push $BOOT_CS64
+ push %ecx
+ lret
+
+.global start_xen_from_efi
+
+#endif /* XEN_BUILD_EFI && CONFIG_SLAUNCH */
+
ENTRY(trampoline_start)
#include "trampoline.S"
ENTRY(trampoline_end)
diff --git a/xen/arch/x86/boot/x86_64.S b/xen/arch/x86/boot/x86_64.S
index 886960c22f..d23cfebdb6 100644
--- a/xen/arch/x86/boot/x86_64.S
+++ b/xen/arch/x86/boot/x86_64.S
@@ -267,14 +267,22 @@ GLOBAL(__page_tables_end)
/* Init pagetables. Enough page directories to map into 4GB. */
.section .init.data.page_aligned, "aw", @progbits

-DATA_LOCAL(l1_bootmap, PAGE_SIZE)
+bootmap_start:
+
+DATA_LOCAL(l1_bootmap, PAGE_SIZE) /* 1x L1 page, mapping 2M of RAM. */
.fill L1_PAGETABLE_ENTRIES, 8, 0
END(l1_bootmap)

-DATA(l2_bootmap, PAGE_SIZE)
+DATA(l2_bootmap, PAGE_SIZE) /* 4x L2 pages, each mapping 1G of RAM. */
.fill 4 * L2_PAGETABLE_ENTRIES, 8, 0
END(l2_bootmap)

-DATA(l3_bootmap, PAGE_SIZE)
+DATA(l3_bootmap, PAGE_SIZE) /* 1x L3 page, mapping the 4x L2 pages. */
.fill L3_PAGETABLE_ENTRIES, 8, 0
END(l3_bootmap)
+
+DATA_LOCAL(l4_bootmap, PAGE_SIZE) /* 1x L4 page, mapping the L3 page. */
+ .fill L4_PAGETABLE_ENTRIES, 8, 0
+END(l4_bootmap)
+
+bootmap_end:
diff --git a/xen/arch/x86/efi/efi-boot.h b/xen/arch/x86/efi/efi-boot.h
index d738b839ee..9653de4ca9 100644
--- a/xen/arch/x86/efi/efi-boot.h
+++ b/xen/arch/x86/efi/efi-boot.h
@@ -7,8 +7,15 @@
#ifndef X86_EFI_EFI_BOOT_H
#define X86_EFI_EFI_BOOT_H

+#include <xen/kernel.h>
#include <xen/vga.h>

+/*
+ * Tell <asm/intel-txt.h> to access TXT registers without address translation
+ * which has not yet been set up.
+ */
+#define __EARLY_SLAUNCH__
+
#include <asm/boot-helpers.h>
#include <asm/e820.h>
#include <asm/edd.h>
@@ -17,8 +24,11 @@
#include <asm/setup.h>
#include <asm/trampoline.h>
#include <asm/efi.h>
+#include <asm/intel-txt.h>
+#include <asm/slaunch.h>

static struct file __initdata ucode;
+static uint64_t __initdata xen_image_size;
static multiboot_info_t __initdata mbi = {
.flags = MBI_MODULES | MBI_LOADERNAME
};
@@ -234,10 +244,31 @@ static void __init efi_arch_pre_exit_boot(void)
}
}

-static void __init noreturn efi_arch_post_exit_boot(void)
+void __init asmlinkage noreturn start_xen_from_efi(void)
{
u64 cr4 = XEN_MINIMAL_CR4 & ~X86_CR4_PGE, efer;

+ if ( slaunch_active )
+ {
+ const struct slr_table *slrt = (const struct slr_table *)efi.slr;

+ const struct slr_entry_hdr *entry;

+

+ entry = slr_next_entry_by_tag(slrt, NULL, SLR_ENTRY_INTEL_INFO);

+ if ( entry != NULL )
+ {
+ const struct slr_entry_intel_info *intel_info =
+ container_of(entry, const struct slr_entry_intel_info, hdr);
+ void *txt_heap = txt_init();
+ const struct txt_os_mle_data *os_mle =
+ txt_start(txt_heap, TXT_OS2MLE);
+ const struct txt_os_sinit_data *os_sinit =
+ txt_start(txt_heap, TXT_OS2SINIT);
+
+ txt_verify_pmr_ranges(os_mle, os_sinit, intel_info, xen_phys_start,
+ xen_phys_start, xen_image_size);
+ }
+ }
+
efi_arch_relocate_image(__XEN_VIRT_START - xen_phys_start);
memcpy(_p(trampoline_phys), trampoline_start, cfg.size);

@@ -283,6 +314,66 @@ static void __init noreturn efi_arch_post_exit_boot(void)
unreachable();
}

+static void __init attempt_secure_launch(void)
+{
+#ifdef CONFIG_SLAUNCH

+ const struct slr_table *slrt;

+ const struct slr_entry_hdr *entry;

+ const struct slr_entry_dl_info *dlinfo;
+ dl_handler_func handler_callback;
+
+ /* The presence of this table indicates a Secure Launch boot. */
+ slrt = (const struct slr_table *)efi.slr;
+ if ( efi.slr == EFI_INVALID_TABLE_ADDR || slrt->magic != SLR_TABLE_MAGIC ||
+ slrt->revision != SLR_TABLE_REVISION )
+ return;
+
+ /* Avoid calls into firmware after DRTM. */
+ __clear_bit(EFI_RS, &efi_flags);
+
+ /*
+ * Make measurements less sensitive to hardware-specific details.
+ *
+ * Intentionally leaving efi_ct and efi_num_ct intact.
+ */
+ efi_ih = NULL;
+ efi_bs = NULL;
+ efi_bs_revision = 0;
+ efi_rs = NULL;
+ efi_version = 0;
+ efi_fw_vendor = NULL;
+ efi_fw_revision = 0;
+ StdOut = NULL;
+ StdErr = NULL;
+ boot_tsc_stamp = 0;
+
+ slaunch_active = true;
+ slaunch_slrt = efi.slr;
+
+ /* Jump through DL stub to initiate Secure Launch. */
+ entry = slr_next_entry_by_tag(slrt, NULL, SLR_ENTRY_DL_INFO);
+ dlinfo = container_of(entry, const struct slr_entry_dl_info, hdr);
+
+ handler_callback = (dl_handler_func)dlinfo->dl_handler;
+ handler_callback(&dlinfo->bl_context);
+
+ unreachable();
+#endif
+}
+
+static void __init noreturn efi_arch_post_exit_boot(void)
+{
+ /*
+ * If Secure Launch happens, attempt_secure_launch() doesn't return and
+ * start_xen_from_efi() is invoked after DRTM has been initiated.
+ * Otherwise, attempt_secure_launch() returns and execution continues as
+ * usual.
+ */
+ attempt_secure_launch();
+
+ start_xen_from_efi();
+}
+
static void __init efi_arch_cfg_file_early(const EFI_LOADED_IMAGE *image,
EFI_FILE_HANDLE *dir_handle,
const char *section)
@@ -783,6 +874,7 @@ static void noreturn __init efi_arch_halt(void)
static void __init efi_arch_load_addr_check(const EFI_LOADED_IMAGE *loaded_image)
{
xen_phys_start = (UINTN)loaded_image->ImageBase;
+ xen_image_size = loaded_image->ImageSize;
if ( (xen_phys_start + loaded_image->ImageSize - 1) >> 32 )
blexit(L"Xen must be loaded below 4Gb.");
if ( xen_phys_start & ((1 << L2_PAGETABLE_SHIFT) - 1) )
diff --git a/xen/arch/x86/efi/fixmlehdr.c b/xen/arch/x86/efi/fixmlehdr.c
new file mode 100644
index 0000000000..60a91c6b73
--- /dev/null
+++ b/xen/arch/x86/efi/fixmlehdr.c
@@ -0,0 +1,127 @@
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+/*
+ * Depending on the toolchain and its configuration the header can end up quite
+ * far from the start of the file.
+ */
+#define PREFIX_SIZE (8*1024)
+
+struct mle_header
+{
+ uint8_t uuid[16];
+ uint32_t header_len;
+ uint32_t version;
+ uint32_t entry_point;
+ uint32_t first_valid_page;
+ uint32_t mle_start;
+ uint32_t mle_end;
+ uint32_t capabilities;
+ uint32_t cmdline_start;
+ uint32_t cmdline_end;
+} __attribute__ ((packed));
+
+static const uint8_t MLE_HEADER_UUID[] = {
+ 0x5a, 0xac, 0x82, 0x90, 0x6f, 0x47, 0xa7, 0x74,
+ 0x0f, 0x5c, 0x55, 0xa2, 0xcb, 0x51, 0xb6, 0x42
+};
+
+int main(int argc, char *argv[])
+{
+ FILE *fp;
+ struct mle_header header;
+ int i;
+ char *end_ptr;
+ long long correction;
+ const char *file_path;
+
+ if ( argc != 3 )
+ {
+ fprintf(stderr, "Usage: %s <xen.efi> <entry-correction>\n", argv[0]);
+ return 1;
+ }
+
+ correction = strtoll(argv[2], &end_ptr, 0);
+ if ( *end_ptr != '\0' )
+ {
+ fprintf(stderr, "Failed to parse '%s' as a number\n", argv[2]);
+ return 1;
+ }
+ if ( correction < INT32_MIN )
+ {
+ fprintf(stderr, "Correction '%s' is too small\n", argv[2]);
+ return 1;
+ }
+ if ( correction > INT32_MAX )
+ {
+ fprintf(stderr, "Correction '%s' is too large\n", argv[2]);
+ return 1;
+ }
+
+ file_path = argv[1];
+
+ fp = fopen(file_path, "r+");
+ if ( fp == NULL )
+ {
+ fprintf(stderr, "Failed to open %s\n", file_path);
+ return 1;
+ }
+
+ for ( i = 0; i < PREFIX_SIZE; i += 16 )
+ {
+ uint8_t bytes[16];
+
+ if ( fread(bytes, sizeof(bytes), 1, fp) != 1 )
+ {
+ fprintf(stderr, "Failed to find MLE header in %s\n", file_path);
+ goto fail;
+ }
+
+ if ( memcmp(bytes, MLE_HEADER_UUID, 16) == 0 )
+ {

+ break;
+ }
+ }
+

+ if ( i >= PREFIX_SIZE )
+ {
+ fprintf(stderr, "Failed to find MLE header in %s\n", file_path);
+ goto fail;
+ }
+
+ if ( fseek(fp, -16, SEEK_CUR) )
+ {
+ fprintf(stderr, "Failed to seek back to MLE header in %s\n", file_path);
+ goto fail;
+ }
+
+ if ( fread(&header, sizeof(header), 1, fp) != 1 )
+ {
+ fprintf(stderr, "Failed to read MLE header from %s\n", file_path);
+ goto fail;
+ }
+
+ if ( fseek(fp, -(int)sizeof(header), SEEK_CUR) )
+ {
+ fprintf(stderr, "Failed to seek back again to MLE header in %s\n",
+ file_path);
+ goto fail;
+ }
+
+ header.entry_point += correction;
+
+ if ( fwrite(&header, sizeof(header), 1, fp) != 1 )
+ {
+ fprintf(stderr, "Failed to write MLE header in %s\n", file_path);
+ goto fail;
+ }
+
+ fclose(fp);
+ return 0;
+
+fail:
+ fclose(fp);
+ return 1;
+}
diff --git a/xen/arch/x86/slaunch.c b/xen/arch/x86/slaunch.c
index af88ca9caa..e506fb4293 100644
--- a/xen/arch/x86/slaunch.c
+++ b/xen/arch/x86/slaunch.c
@@ -6,6 +6,7 @@
*/

#include <xen/compiler.h>
+#include <xen/efi.h>
#include <xen/init.h>
#include <xen/kernel.h>
#include <xen/macros.h>
@@ -252,10 +253,23 @@ check_drtm_policy(const struct slr_table *slrt,
{
uint32_t i;
uint32_t num_mod_entries;
+ int min_entries;

- if ( policy->nr_entries < 2 )
- panic("DRTM policy in SLRT contains less than 2 entries (%d)!\n",
- policy->nr_entries);
+ min_entries = efi_enabled(EFI_BOOT) ? 1 : 2;
+ if ( policy->nr_entries < min_entries )
+ {
+ panic("DRTM policy in SLRT contains less than %d entries (%d)!\n",
+ min_entries, policy->nr_entries);
+ }
+
+ if ( efi_enabled(EFI_BOOT) )
+ {
+ check_slrt_policy_entry(&policy_entry[0], 0, slrt);
+ /* SLRT was measured in slaunch_measure_slrt(). */
+ return 1;
+ }
+
+ /* This must be legacy MultiBoot2 boot. */

/*

* MBI policy entry must be the first one, so that measuring order matches

@@ -324,6 +338,7 @@ void __init slaunch_process_drtm_policy(const struct boot_info *bi)
const struct slr_table *slrt;
const struct slr_entry_policy *policy;
struct slr_policy_entry *policy_entry;
+ int rc;
uint16_t i;
unsigned int measured;

@@ -338,7 +353,6 @@ void __init slaunch_process_drtm_policy(const struct boot_info *bi)

for ( i = measured; i < policy->nr_entries; i++ )

{
- int rc;

uint64_t start = policy_entry[i].entity;

uint64_t size = policy_entry[i].size;

@@ -384,6 +398,59 @@ void __init slaunch_process_drtm_policy(const struct boot_info *bi)

policy_entry[i].flags |= SLR_POLICY_FLAG_MEASURED;
}

+
+ /*
+ * On x86 EFI platforms Xen reads its command-line options and kernel/initrd
+ * from configuration files (several can be chained). Bootloader can't know
+ * contents of the configuration beforehand without parsing it, so there
+ * will be no corresponding policy entries. Instead, measure command-line
+ * and all modules here.
+ */
+ if ( efi_enabled(EFI_BOOT) )
+ {
+#define LOG_DATA(str) (uint8_t *)(str), (sizeof(str) - 1)
+
+ slaunch_hash_extend(DRTM_LOC, DRTM_DATA_PCR,
+ (const uint8_t *)bi->cmdline, strlen(bi->cmdline),
+ DLE_EVTYPE_SLAUNCH, LOG_DATA("Xen's command line"));

+
+ for ( i = 0; i < bi->nr_modules; i++ )
+ {

+ const struct boot_module *mod = &bi->mods[i];
+

+ paddr_t string = mod->arch.cmdline_pa;
+ paddr_t start = mod->start;
+ size_t size = mod->size;
+
+ if ( mod->arch.relocated || mod->arch.released )
+ {
+ panic("A module \"%s\" (#%d) was consumed before measurement\n",
+ (const char *)__va(string), i);
+ }
+
+ /*
+ * Measuring module's name separately because module's command-line
+ * parameters are appended to its name when present.
+ *
+ * 2 MiB is minimally mapped size and it should more than suffice.
+ */
+ rc = slaunch_map_l2(string, 2 * 1024 * 1024);

+ BUG_ON(rc != 0);
+

+ slaunch_hash_extend(DRTM_LOC, DRTM_DATA_PCR,
+ __va(string), strlen(__va(string)),
+ DLE_EVTYPE_SLAUNCH,
+ LOG_DATA("MB module string"));

+
+ rc = slaunch_map_l2(start, size);
+ BUG_ON(rc != 0);
+

+ slaunch_hash_extend(DRTM_LOC, DRTM_CODE_PCR, __va(start), size,
+ DLE_EVTYPE_SLAUNCH, LOG_DATA("MB module"));
+ }
+
+#undef LOG_DATA

+ }
}

int __init slaunch_map_l2(paddr_t paddr, size_t size)

diff --git a/xen/common/efi/boot.c b/xen/common/efi/boot.c
index 8f24df9bc2..41ccc6dcd3 100644
--- a/xen/common/efi/boot.c
+++ b/xen/common/efi/boot.c
@@ -19,6 +19,7 @@
#if EFI_PAGE_SIZE != PAGE_SIZE
# error Cannot use xen/pfn.h here!
#endif
+#include <xen/slr-table.h>
#include <xen/string.h>
#include <xen/stringify.h>
#ifdef CONFIG_X86
@@ -45,6 +46,8 @@
#define EFI_SYSTEM_RESOURCE_TABLE_GUID \
{ 0xb122a263U, 0x3661, 0x4f68, {0x99, 0x29, 0x78, 0xf8, 0xb0, 0xd6, 0x21, 0x80} }
#define EFI_SYSTEM_RESOURCE_TABLE_FIRMWARE_RESOURCE_VERSION 1
+#define UEFI_SLR_TABLE_GUID \
+ { 0x877a9b2aU, 0x0385, 0x45d1, { 0xa0, 0x34, 0x9d, 0xac, 0x9c, 0x9e, 0x56, 0x5f } }

typedef struct {
EFI_GUID FwClass;
@@ -1154,6 +1157,7 @@ static void __init efi_tables(void)
static EFI_GUID __initdata mps_guid = MPS_TABLE_GUID;
static EFI_GUID __initdata smbios_guid = SMBIOS_TABLE_GUID;
static EFI_GUID __initdata smbios3_guid = SMBIOS3_TABLE_GUID;
+ static EFI_GUID __initdata slr_guid = UEFI_SLR_TABLE_GUID;

if ( match_guid(&acpi2_guid, &efi_ct[i].VendorGuid) )
efi.acpi20 = (unsigned long)efi_ct[i].VendorTable;
@@ -1165,6 +1169,8 @@ static void __init efi_tables(void)
efi.smbios = (unsigned long)efi_ct[i].VendorTable;
if ( match_guid(&smbios3_guid, &efi_ct[i].VendorGuid) )
efi.smbios3 = (unsigned long)efi_ct[i].VendorTable;
+ if ( match_guid(&slr_guid, &efi_ct[i].VendorGuid) )
+ efi.slr = (unsigned long)efi_ct[i].VendorTable;
if ( match_guid(&esrt_guid, &efi_ct[i].VendorGuid) )
esrt = (UINTN)efi_ct[i].VendorTable;
}
diff --git a/xen/common/efi/runtime.c b/xen/common/efi/runtime.c
index 596f2710fb..b2cebaad02 100644
--- a/xen/common/efi/runtime.c
+++ b/xen/common/efi/runtime.c
@@ -72,6 +72,7 @@ struct efi __read_mostly efi = {
.mps = EFI_INVALID_TABLE_ADDR,
.smbios = EFI_INVALID_TABLE_ADDR,
.smbios3 = EFI_INVALID_TABLE_ADDR,
+ .slr = EFI_INVALID_TABLE_ADDR,
};

const struct efi_pci_rom *__read_mostly efi_pci_roms;
diff --git a/xen/include/xen/efi.h b/xen/include/xen/efi.h
index 87146172ad..37d016d885 100644
--- a/xen/include/xen/efi.h
+++ b/xen/include/xen/efi.h
@@ -17,6 +17,7 @@ struct efi {
unsigned long acpi20; /* ACPI table (ACPI 2.0) */
unsigned long smbios; /* SM BIOS table */
unsigned long smbios3; /* SMBIOS v3 table */
+ unsigned long slr; /* SLR table */
};

extern struct efi efi;
--
2.55.0

[Sergii Dmytruk]

From: Szymon Acedański <ac...@invisiblethingslab.com>

Pointer to txt_os_sinit_data variables lost constness due to the use of
txt_find_ext_data_element() which needs to work in a non-const context
as well for its other use.

This is required for modern Intel CPUs (at least LunarLake) that no
longer support PMR (Protected Memory Regions) protection mechanism.
Unlike PMR, TPR is not related to Intel VT-d, independent from IOMMU
and, despite its name, is not tied to TXT.

The next generation (PantherLake) similarly supports only PMR but seems
to have an undocumented requirement that TPR protection must be disabled
or device initialization fails (NVMe/USB/NIC). This is not done by this
patch.

Signed-off-by: Szymon Acedański <ac...@invisiblethingslab.com>
Assisted-by: Claude:claude-opus-4-7

Signed-off-by: Sergii Dmytruk <sergii....@3mdeb.com>
---

Notes:

v4: new commit in this version, needed for modern devices

xen/arch/x86/boot/head.S | 4 +-
xen/arch/x86/boot/slaunch-early.c | 6 +-
xen/arch/x86/efi/efi-boot.h | 7 +-
xen/arch/x86/include/asm/intel-txt.h | 182 +++++++++++++++++++++------
4 files changed, 151 insertions(+), 48 deletions(-)

diff --git a/xen/arch/x86/boot/head.S b/xen/arch/x86/boot/head.S
index 22b331a45c..ac177839d1 100644
--- a/xen/arch/x86/boot/head.S
+++ b/xen/arch/x86/boot/head.S
@@ -136,12 +136,12 @@ SYM(mle_header, DATA, LOCAL, 16)

.long 0xa2555c0f /* UUID2 */

.long 0x42b651cb /* UUID3 */

.long (.Lmle_header_end - mle_header) /* MLE header size */

- .long 0x00020002 /* MLE version 2.2 */
+ .long 0x00020003 /* MLE version 2.3 */

.long (slaunch_stub_entry - start) /* Linear entry point of MLE (SINIT virt. address) */

.long 0x00000000 /* First valid page of MLE */

.long 0x00000000 /* Offset within binary of first byte of MLE */

.long (__base_relocs_end - start) /* Offset within binary of last byte + 1 of MLE */

- .long 0x00000723 /* Bit vector of MLE-supported capabilities */
+ .long 0x00004723 /* Bit vector of MLE-supported capabilities */

.long 0x00000000 /* Starting linear address of command line (unused) */

.long 0x00000000 /* Ending linear address of command line (unused) */

.Lmle_header_end:
diff --git a/xen/arch/x86/boot/slaunch-early.c b/xen/arch/x86/boot/slaunch-early.c
index 9b16602ac8..7348a3d156 100644
--- a/xen/arch/x86/boot/slaunch-early.c
+++ b/xen/arch/x86/boot/slaunch-early.c
@@ -35,7 +35,7 @@ void asmlinkage slaunch_early_init(uint32_t load_base_addr,

void *txt_heap;
const struct txt_os_mle_data *os_mle;
const struct slr_table *slrt;

- const struct txt_os_sinit_data *os_sinit;
+ struct txt_os_sinit_data *os_sinit;
const struct slr_entry_hdr *entry;

const struct slr_entry_intel_info *intel_info;
uint32_t size = tgt_end_addr - tgt_base_addr;

@@ -99,6 +99,6 @@ void asmlinkage slaunch_early_init(uint32_t load_base_addr,

result->mbi_pa = intel_info->boot_params_base;

- txt_verify_pmr_ranges(os_mle, os_sinit, intel_info,
- load_base_addr, tgt_base_addr, size);
+ txt_verify_dma_protection(os_mle, os_sinit, intel_info,
+ load_base_addr, tgt_base_addr, size);
}
diff --git a/xen/arch/x86/efi/efi-boot.h b/xen/arch/x86/efi/efi-boot.h
index 9653de4ca9..573d1938c6 100644
--- a/xen/arch/x86/efi/efi-boot.h
+++ b/xen/arch/x86/efi/efi-boot.h
@@ -261,11 +261,12 @@ void __init asmlinkage noreturn start_xen_from_efi(void)
void *txt_heap = txt_init();

const struct txt_os_mle_data *os_mle =

txt_start(txt_heap, TXT_OS2MLE);
- const struct txt_os_sinit_data *os_sinit =
+ struct txt_os_sinit_data *os_sinit =
txt_start(txt_heap, TXT_OS2SINIT);

- txt_verify_pmr_ranges(os_mle, os_sinit, intel_info, xen_phys_start,
- xen_phys_start, xen_image_size);
+ txt_verify_dma_protection(os_mle, os_sinit, intel_info,
+ xen_phys_start, xen_phys_start,
+ xen_image_size);
}
}

diff --git a/xen/arch/x86/include/asm/intel-txt.h b/xen/arch/x86/include/asm/intel-txt.h
index eb15bf68ad..0fd2fb6fdd 100644
--- a/xen/arch/x86/include/asm/intel-txt.h
+++ b/xen/arch/x86/include/asm/intel-txt.h
@@ -65,6 +65,12 @@
#define SLAUNCH_ERROR_NO_VENDOR_INFO 0xc0008009U
#define SLAUNCH_ERROR_BAD_VENDOR_INFO 0xc000800AU
#define SLAUNCH_ERROR_BAD_SLRT_ADDRESS 0xc000800BU
+#define SLAUNCH_ERROR_TPR_INVALID 0xc000800CU
+#define SLAUNCH_ERROR_TPR_UNSUPPORTED 0xc000800DU
+#define SLAUNCH_ERROR_TPR_NOT_FOUND 0xc000800EU
+
+/* SINIT/MLE capability bit for TPR (TXT Protected Range) DMA protection. */
+#define TXT_SINIT_MLE_CAP_TPR_SUPPORT 14

#ifndef __ASSEMBLER__

@@ -253,6 +259,19 @@ struct heap_event_log_pointer_element2_1 {
uint32_t next_record_offset;
} __packed;

+/*
+ * Extended data describing TPR (TXT Protected Range) DMA protection ranges.
+ */
+struct txt_heap_tpr_range {
+ uint64_t base;
+ uint64_t size;
+} __packed;
+
+struct txt_heap_tpr_req_element {
+ uint32_t count;
+ struct txt_heap_tpr_range ranges[0];

+} __packed;
+
/*
* Functions to extract data from the Intel TXT Heap Memory.
*

@@ -342,67 +361,150 @@ txt_find_ext_data_element(struct txt_os_sinit_data *os_sinit, uint32_t type)
return NULL;
}

-static inline bool is_in_pmr(const struct txt_os_sinit_data *os_sinit,
- uint64_t base, uint32_t size, bool check_high)
+static inline bool is_in_dma_prot(struct txt_os_sinit_data *os_sinit,
+ uint64_t base, uint32_t size, bool check_high)
{
+ uint64_t lo_size, hi_base, hi_size;

+
/* Check for size overflow. */

if ( base + size < base )

txt_reset(SLAUNCH_ERROR_INTEGER_OVERFLOW);

+ if ( os_sinit->capabilities & (1u << TXT_SINIT_MLE_CAP_TPR_SUPPORT) )
+ {
+ /*
+ * txt_verify_dma_protection() has already validated presence and contents
+ * of the TPR_REQ element.
+ */
+ const struct txt_heap_tpr_req_element *tpr_req = (const struct txt_heap_tpr_req_element *)
+ txt_find_ext_data_element(os_sinit, TXT_HEAP_EXTDATA_TYPE_TPR_REQ)->data;
+
+ lo_size = tpr_req->ranges[0].size;
+ if ( tpr_req->count > 1 )
+ {
+ hi_base = tpr_req->ranges[1].base;
+ hi_size = tpr_req->ranges[1].size;
+ }
+ else
+ {
+ hi_base = 0;
+ hi_size = 0;
+ }
+ }
+ else
+ {
+ lo_size = os_sinit->vtd_pmr_lo_size;
+ hi_base = os_sinit->vtd_pmr_hi_base;
+ hi_size = os_sinit->vtd_pmr_hi_size;
+ }
+
/*
- * txt_verify_pmr_ranges() makes sure the low range always starts at 0, so
- * its size is also end address.
+ * txt_verify_dma_protection() makes sure the low range always starts at
+ * 0, so its size is also end address.
*/
- if ( base + size <= os_sinit->vtd_pmr_lo_size )
+ if ( base + size <= lo_size )
return true;

- if ( check_high && os_sinit->vtd_pmr_hi_size != 0 )
+ if ( check_high && hi_size != 0 )
{
- if ( base >= os_sinit->vtd_pmr_hi_base &&
- base + size <= os_sinit->vtd_pmr_hi_base +
- os_sinit->vtd_pmr_hi_size )
+ if ( base >= hi_base && base + size <= hi_base + hi_size )
return true;
}

return false;
}

-static inline void txt_verify_pmr_ranges(
+static inline void txt_verify_dma_protection(
const struct txt_os_mle_data *os_mle,
- const struct txt_os_sinit_data *os_sinit,
+ struct txt_os_sinit_data *os_sinit,
const struct slr_entry_intel_info *info,
uint32_t load_base_addr,
uint32_t tgt_base_addr,
uint32_t xen_size)
{
- bool check_high_pmr = false;
+ bool check_high = false;

- /* Verify the value of the low PMR base. It should always be 0. */
- if ( os_sinit->vtd_pmr_lo_base != 0 )
- txt_reset(SLAUNCH_ERROR_LO_PMR_BASE);
+ if ( os_sinit->capabilities & (1u << TXT_SINIT_MLE_CAP_TPR_SUPPORT) )
+ {
+ const struct txt_ext_data_element *tpr_req_data_element;
+ const struct txt_heap_tpr_req_element *tpr_req;

- /*
- * Low PMR size should not be 0 on current platforms. There is an ongoing
- * transition to TPR-based DMA protection instead of PMR-based; this is not
- * yet supported by the code.
- */
- if ( os_sinit->vtd_pmr_lo_size == 0 )
- txt_reset(SLAUNCH_ERROR_LO_PMR_SIZE);
+ /*
+ * For TPR-based DMA protection, it's not specified that the low
+ * range must begin at address 0. For now though, we support only
+ * 1- and 2-range configurations with the low range starting at 0.
+ */

- /* Check if regions overlap. Treat regions with no hole between as error. */
- if ( os_sinit->vtd_pmr_hi_size != 0 &&
- os_sinit->vtd_pmr_hi_base <= os_sinit->vtd_pmr_lo_size )
- txt_reset(SLAUNCH_ERROR_HI_PMR_BASE);
+ tpr_req_data_element = txt_find_ext_data_element(os_sinit, TXT_HEAP_EXTDATA_TYPE_TPR_REQ);
+ if ( tpr_req_data_element == NULL )
+ txt_reset(SLAUNCH_ERROR_TPR_NOT_FOUND);
+ if ( tpr_req_data_element->size < sizeof(struct txt_heap_tpr_req_element) )
+ txt_reset(SLAUNCH_ERROR_TPR_INVALID);
+ tpr_req = (const struct txt_heap_tpr_req_element *)tpr_req_data_element->data;
+ if ( tpr_req->count < 1 )
+ txt_reset(SLAUNCH_ERROR_TPR_INVALID);
+ if ( tpr_req->count > 2 )
+ txt_reset(SLAUNCH_ERROR_TPR_UNSUPPORTED);
+
+ /* Low range must start at 0. */
+ if ( tpr_req->ranges[0].base != 0 )
+ txt_reset(SLAUNCH_ERROR_TPR_UNSUPPORTED);
+
+ /* Size must not be 0. */
+ if ( tpr_req->ranges[0].size == 0 )
+ txt_reset(SLAUNCH_ERROR_TPR_INVALID);
+
+ if ( tpr_req->count > 1 )
+ {
+ /* Size must not be 0. */
+ if ( tpr_req->ranges[1].size == 0 )
+ txt_reset(SLAUNCH_ERROR_TPR_INVALID);
+
+ /* Ranges must not overlap. */
+ if ( tpr_req->ranges[0].size > tpr_req->ranges[1].base )
+ txt_reset(SLAUNCH_ERROR_TPR_INVALID);
+
+ /* Overflow check. */
+ if ( tpr_req->ranges[1].base + tpr_req->ranges[1].size < tpr_req->ranges[1].size )

+ txt_reset(SLAUNCH_ERROR_INTEGER_OVERFLOW);
+
+ /* All regions accessed by 32b code must be below 4G. */

+ if ( tpr_req->ranges[1].base + tpr_req->ranges[1].size <=
+ 0x100000000ULL )
+ check_high = true;
+ }
+ }
+ else
+ {

+ /* Verify the value of the low PMR base. It should always be 0. */
+ if ( os_sinit->vtd_pmr_lo_base != 0 )
+ txt_reset(SLAUNCH_ERROR_LO_PMR_BASE);

- /* Check for size overflow. */
- if ( os_sinit->vtd_pmr_hi_base + os_sinit->vtd_pmr_hi_size <
- os_sinit->vtd_pmr_hi_size )
- txt_reset(SLAUNCH_ERROR_INTEGER_OVERFLOW);
+ /*
+ * Low PMR size should not be 0 on current platforms when PMR mode is
+ * in use.
+ */

+ if ( os_sinit->vtd_pmr_lo_size == 0 )
+ txt_reset(SLAUNCH_ERROR_LO_PMR_SIZE);

- /* All regions accessed by 32b code must be below 4G. */
- if ( os_sinit->vtd_pmr_hi_base + os_sinit->vtd_pmr_hi_size <=
- 0x100000000ULL )
- check_high_pmr = true;
+ /*
+ * Check if regions overlap. Treat regions with no hole between as
+ * error.
+ */

+ if ( os_sinit->vtd_pmr_hi_size != 0 &&
+ os_sinit->vtd_pmr_hi_base <= os_sinit->vtd_pmr_lo_size )
+ txt_reset(SLAUNCH_ERROR_HI_PMR_BASE);
+
+ /* Check for size overflow. */
+ if ( os_sinit->vtd_pmr_hi_base + os_sinit->vtd_pmr_hi_size <
+ os_sinit->vtd_pmr_hi_size )
+ txt_reset(SLAUNCH_ERROR_INTEGER_OVERFLOW);
+
+ /* All regions accessed by 32b code must be below 4G. */
+ if ( os_sinit->vtd_pmr_hi_base + os_sinit->vtd_pmr_hi_size <=
+ 0x100000000ULL )

+ check_high = true;
+ }

/*

* ACM checks that TXT heap and MLE memory is protected against DMA. We have

@@ -412,12 +514,12 @@ static inline void txt_verify_pmr_ranges(
*/

/* Check if all of Xen before relocation is protected. */

- if ( !is_in_pmr(os_sinit, load_base_addr, xen_size, check_high_pmr) )
+ if ( !is_in_dma_prot(os_sinit, load_base_addr, xen_size, check_high) )
txt_reset(SLAUNCH_ERROR_LO_PMR_MLE);

/* Check if all of Xen after relocation is protected. */

if ( load_base_addr != tgt_base_addr &&

- !is_in_pmr(os_sinit, tgt_base_addr, xen_size, check_high_pmr) )
+ !is_in_dma_prot(os_sinit, tgt_base_addr, xen_size, check_high) )
txt_reset(SLAUNCH_ERROR_LO_PMR_MLE);

/* If present, check that MBI is protected. */

@@ -426,8 +528,8 @@ static inline void txt_verify_pmr_ranges(
const multiboot2_fixed_t *mbi =
(const multiboot2_fixed_t *)(uintptr_t)info->boot_params_base;

- if ( !is_in_pmr(os_sinit, info->boot_params_base, mbi->total_size,
- check_high_pmr) )
+ if ( !is_in_dma_prot(os_sinit, info->boot_params_base, mbi->total_size,
+ check_high) )
txt_reset(SLAUNCH_ERROR_BUFFER_BEYOND_PMR);
}

@@ -451,8 +553,8 @@ static inline void txt_verify_pmr_ranges(
*/
/*

if ( os_mle->evtlog_addr != 0 && os_mle->evtlog_size != 0 &&

- !is_in_pmr(os_sinit, os_mle->evtlog_addr, os_mle->evtlog_size,
- check_high_pmr) )
+ !is_in_dma_prot(os_sinit, os_mle->evtlog_addr, os_mle->evtlog_size,
+ check_high) )
txt_reset(SLAUNCH_ERROR_BUFFER_BEYOND_PMR);
*/
}
--
2.55.0

[Sergii Dmytruk]

Signed-off-by: Sergii Dmytruk <sergii....@3mdeb.com>
---

Notes:

v4: updated list of files to match this patchset

MAINTAINERS | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index ed0ffa608f..54c0428f8d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -565,6 +565,25 @@ F: */configure
F: */*.ac
F: tools/

+TRENCHBOOT SECURE LAUNCH
+R: Daniel P. Smith <dps...@apertussolutions.com>
+R: Ross Philipson <ross.ph...@gmail.com>
+R: Sergii Dmytruk <sergii....@3mdeb.com>
+S: Supported
+F: xen/arch/x86/boot/slaunch-early.c
+F: xen/arch/x86/efi/fixmlehdr.c
+F: xen/arch/x86/include/asm/intel-txt.h
+F: xen/arch/x86/include/asm/slaunch-tpm.h
+F: xen/arch/x86/include/asm/slaunch.h
+F: xen/arch/x86/include/asm/tpm.h
+F: xen/arch/x86/include/asm/tpm1.h
+F: xen/arch/x86/include/asm/tpm2.h
+F: xen/arch/x86/intel-txt.c
+F: xen/arch/x86/slaunch-tpm.c
+F: xen/arch/x86/slaunch.c
+F: xen/arch/x86/tpm.c
+F: xen/include/xen/slr-table.h
+
VM EVENT, MEM ACCESS and MONITOR
M: Tamas K Lengyel <ta...@tklengyel.com>
S: Supported
--
2.55.0