Xilinx Ddr4 Ip

[Odon Irving]

Consideran RF application that requires accessing external DDR4 memory to capture RF samples at a high data rate. In this example, the design task is to design a control algorithm that writes and reads captured RF samples from the external PL DDR4 memory. To verify RF samples captured on the DDR4, send a sinusoid tone from the FPGA to the digital-to-analog converter (DAC) of the RF Data Converter (RFDC) block (output of the DAC is looped back to the ADC input), and receive the data back on the FPGA. The following are the system specifications.

Create an SoC model soc_ddr4datacapture_top as the top model and set the hardware board to Xilinx Zynq Ultrascale+ RFSoC ZCU111 evaluation kit. This model includes the FPGA model soc_ddr4datacapture_fpga and the processor model soc_soc_ddr4datacapture_proc, which are instantiated as model references. The top model also includes the AXI4-Stream to Software and AXI4 Random Access Memory blocks, which share the external memory between the FPGA and the processor.

An RFSoC device has its RF data converter connected to the programmable logic. To configure the ADC and DAC settings, use the RFDC block. The block provides an interface to the Xilinx RF Data Converter IP in Simulink for modeling a wireless system destined for implementation on Xilinx RFSoC device.

To meet the system requirement of 2048 MSPS as the data rate for DACs and ADCs, you must choose the values of the Interpolation mode, Decimation mode, and Samples per clock cycle parameters such that the effective clock cycle (sample rate) for the wireless algorithm FPGA is in the desirable range. The parameter values are displayed on the block under Stream clock frequency after you click Apply.

In the DAC Tone Generation subsystem, four consecutive samples of the sinusoid waveform are generated in parallel by using four HDL Optimized NCO blocks. Each HDL Optimized NCO block has a different offset. The four samples comprise 64 bits of data and have the same width as AXI-Stream data.

The ADC Capture subsystem uses a trigger and the DDR4 capture logic to capture ADC RF samples and write them to the DDR4 memory frame by frame. After the write operation is complete, the subsystem reads and sends the data to the processor to display the captured signal. The register, triggerFreq from the processor controls the trigger and capture logic.

The processor logic contains an event-based task driven by the arrival of data from the FPGA through the DDR memory. The processor algorithm task is denoted as dataTask in the Task Manager block and is specified as event driven. The Task Manager block schedules data asynchronously by means of the buffer ready event rdEvent in the memory, denoting the arrival of a frame of data from the FPGA. The algorithm itself is modeled under the Processor Algorithm Wrapper subsystem in the processor model soc_ddr4datacapture_proc and connected to the Task Manager block at the top level. To operate on the data received as a frame of four packed samples with the uint64 data type, you must first unpack and restore the signedness of the data. The output of the Processor Algorithm Wrapper subsystem is then connected to the Spectrum and Time scope for visualization. In a separate Initialize Function subsystem, various registers on the FPGA subsystems are initialized with their default values.

The waveform is looped back from the FPGA to the processor through the RFDC block, the ADC Capture subsystem in FPGA, and the DDR4 memory block for capturing the waveform. In the processor system, the waveform is visualized in the frequency domain using a Spectrum scope block named ADC Captured Signal. The data is observed on the spectrum scope with a substantial delay after the start of the simulation. This delay is because of the delay in the availability of the first frame of data through the DDR4 to the scope, which is due to the length of the loopback data path.

To implement the model on a supported SoC board, use the SoC Builder tool. Ensure that the Hardware Board is set to Xilinx Zynq UltraScale+ RFSoC ZCU111 Evaluation Kit in the System on Chip tab of the Simulink toolstrip.

On the Connect Hardware screen, test the connectivity of the host computer with the SoC board by clicking Test Connection. To go to the Run Application screen, click Next.

Run the model in external mode by clicking Monitor & Tune. You can control the configuration from the Simulink model. Copy the spectrum analyzer from the top model and connect to the rate transition block as shown in this figure, and run the model. You can observe the received signal waveform of 5 MHz in the spectrum analyzer.

This example shows how to design a system to write and read the captured RF samples from external DDR4 memory. You simulated and deployed the design on the Xilinx Zynq UltraScale+ ZCU111 evaluation kit using SoC Blockset. You can use this example as a reference for designing your application that requires DDR4 for data capture.

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