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With new Tru64 UNIX capabilities, Compaq continues to enhance its operating environment, adding powerful workload management, increasing transaction availability with support for on-line add-and-replacement of processors, lowering the entry cost of proven clusters technology by supporting industry-standard cluster interconnects, and becoming the first company to offer customers the ability to mix 64-bit CPU speeds within a single system.
HP also has integrated the XP arrays with HP OpenView data center and storage management software. This allows information technology (IT) professionals to deliver availability and performance service level agreements to their users. In addition, HP provides pre-tested storage solutions such as disaster recovery, remote clustering, and zero-downtime backup with the XP arrays that allow IT administrators to quickly deploy storage solutions in heterogeneous server environments.
Bull Infrastructure & Systems has announced its new line of Escala IL enterprise servers based on the Intel(R) Itanium(TM) architecture, and unveiled 4-way and 16-way models in this product line. Bull will offer these new servers with a comprehensive set of market programs and services called i-scale Attitude. i-scale Attitude gives software developers and early technology adopters a head start with the new 64-bit enterprise computing environment offered by new Escala IL servers based on the Intel(R) Itanium(TM) architecture.
Bull will offer the Escala IL400R with a choice of three supported operating systems: 64-bit Linux(R), Microsoft(R) Windows(R) Whistler Server and AIX 5L(TM). The Escala IL400R server includes comprehensive reliability features such as hot-pluggable, redundant power supplies and fans.
Derived from proven technologies developed for Unix(R) based operating systems, accounting for over 800,000 users worldwide, the NeTraverse Server Standard Edition technology currently supports over one hundred concurrent users at the German Railway, providing a Linux alternative to the Citrix-style server-based thin-client computing model. NSSE will run on an office LAN as well as in a data center serving applications over the Internet and is ideally suited for task-based workers in the professional office, small to mid-size business, government agency, university, and departmental or branch office.
Sixty-four bit architectures have become a key issue in the mechanical computer-aided design and manufacturing (CAD/CAM) market as product development engineers work on larger and more complex data sets. The 64-bit environment allows users to process large amounts of data and run engineering applications by allowing significantly more address space than previous technology.
3.4 Another embodiment, shown in figure 2 and explained in the timing diagrams shown in figures 6 and 7, does however satisfy the independent claims as originally filed. It concerns two MAC operators connected in series. The structure of the circuit differs from that of the figure 1 in that result values "E" are not written to memory but instead are fed to an input of the second MAC operator 121. For the purposes of this decision only the operation of the first MAC operator 111 need be considered. Each of the input values "A", "B" and "C" is read from a memory and stored in a separate register (112, 113 and 114, respectively) before being fed to the first MAC operator 111. As to the outputs of the first MAC operator, output "D" is stored in register 115 before being fed back as an input, and output "E" is stored in register 124 before being fed to the second MAC operator 121. A word (W) is defined as being 32 bits (see page 26, line 9), while the memory access width is 64 bits i.e. 2W (see page 18, line 26, to page 19, line 2). The description also states (at page 35, line 26, to page 36, line 1), as pointed out by the appellant, that the MAC operator produces three 64-bit memory reads and one 64-bit memory write within a four-clock period. Thus the board agrees with the appellant that the memory shown in figure 2 offers a data transfer speed of 64 bits, i.e. 2W per clock cycle. In this case in the inner loop 16 "B" bits (i.e. W/2) and 16 "C" bits (i.e. W/2) are read in by the MAC operator and 16 "E" bits (i.e. W/2) are written by the MAC operator in each clock cycle. Thus the inner loop runs at 16 + 16 + 16 = 48 bits (i.e. 1.5W) per clock cycle. As the memory allows a data transfer speed of 64 bits (i.e. 2W) per clock cycle, the inner loop runs below the transfer speed provided by the memory. The skilled person would understand that the remaining memory access capacity of 16 bits (i.e. 0.5W) per clock cycle would be occupied by fetching "A" from the memory in the outer loop.
3.5 According to both independent claims as originally filed and the description (see page 13, lines 7 to 13, page 35, line 25, to page 36, line 5, and page 45, line 25, to page 46, line 4), the total amount of data supplied in each clock cycle is adjusted such that total amount of data consumed and produced by the MAC operator in one clock cycle is equal to or smaller than the maximum amount of data that the memory can transfer in one clock cycle. Put another way, the MAC operator never has to wait for the memory. The skilled person would have understood the total amount of data consumed and produced by the MAC operator in one clock cycle to include both the inner and outer loops of the algorithm and thus to include the reading of variables "a", "b" and "c" (or "A", "B" and "C") from memory, as well as the writing of the result "e" (or "E") to memory. As is stated in the description, and has been relied upon by the appellant, in the embodiment shown in figure 2 the MAC operator produces three 64-bit memory reads (i.e. "A", "B" and "C") and one 64-bit memory write (i.e. the result "E") within a four-clock period. In other words, in the application as originally filed the references to the total amount of data consumed and produced by the MAC operator in one clock cycle included not only the inner loop but also the outer loop of the calculation algorithm. This embodiment satisfies the associated condition.
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