64 Bits Checker

[Glendora Spink]

Aparity bit, or check bit, is a bit added to a string of binary code. Parity bits are a simple form of error detecting code. Parity bits are generally applied to the smallest units of a communication protocol, typically 8-bit octets (bytes), although they can also be applied separately to an entire message string of bits.

The parity bit ensures that the total number of 1-bits in the string is even or odd.[1] Accordingly, there are two variants of parity bits: even parity bit and odd parity bit. In the case of even parity, for a given set of bits, the bits whose value is 1 are counted. If that count is odd, the parity bit value is set to 1, making the total count of occurrences of 1s in the whole set (including the parity bit) an even number. If the count of 1s in a given set of bits is already even, the parity bit's value is 0. In the case of odd parity, the coding is reversed. For a given set of bits, if the count of bits with a value of 1 is even, the parity bit value is set to 1 making the total count of 1s in the whole set (including the parity bit) an odd number. If the count of bits with a value of 1 is odd, the count is already odd so the parity bit's value is 0. Even parity is a special case of a cyclic redundancy check (CRC), where the 1-bit CRC is generated by the polynomial x+1.

In telecommunications the parity referred to by some protocols is for error-detection. The transmission medium is preset, at both end points, to agree on either odd parity or even parity. For each string of bits ready to transmit (data packet) the sender calculates its parity bit, zero or one, to make it conform to the agreed parity, even or odd. The receiver of that packet first checks that the parity of the packet as a whole is in accordance with the preset agreement, then, if there was a parity error in that packet, requests a retransmission of that packet.

In computer science the parity stripe or parity disk in a RAID provides error-correction. Parity bits are written at the rate of one parity bit per n bits, where n is the number of disks in the array. When a read error occurs, each bit in the error region is recalculated from its set of n bits. In this way, using one parity bit creates "redundancy" for a region from the size of one bit to the size of one disk. See Redundant Array of Independent Disks below.

In electronics, transcoding data with parity can be very efficient, as XOR gates output what is equivalent to a check bit that creates an even parity, and XOR logic design easily scales to any number of inputs. XOR and AND structures comprise the bulk of most integrated circuitry.

If an odd number of bits (including the parity bit) are transmitted incorrectly, the parity bit will be incorrect, thus indicating that a parity error occurred in the transmission. The parity bit is suitable only for detecting errors; it cannot correct any errors, as there is no way to determine the particular bit that is corrupted. The data must be discarded entirely, and retransmitted from scratch. On a noisy transmission medium, successful transmission can therefore take a long time or even never occur. However, parity has the advantage that it uses only a single bit and requires only a number of XOR gates to generate. See Hamming code for an example of an error-correcting code.

This mechanism enables the detection of single bit errors, because if one bit gets flipped due to line noise, there will be an incorrect number of ones in the received data. In the two examples above, Bob's calculated parity value matches the parity bit in its received value, indicating there are no single bit errors. Consider the following example with a transmission error in the second bit using XOR:

There is a limitation to parity schemes. A parity bit is guaranteed to detect only an odd number of bit errors. If an even number of bits have errors, the parity bit records the correct number of ones even though the data is corrupt. (See also error detection and correction.) Consider the same example as before but with an even number of corrupted bits:

Because of its simplicity, parity is used in many hardware applications in which an operation can be repeated in case of difficulty, or simply detecting the error is helpful. For example, the SCSI and PCI buses use parity to detect transmission errors, and many microprocessor instruction caches include parity protection. Because the Instruction cache data is just a copy of the main memory, it can be disregarded and refetched if it is found to be corrupted.

In serial data transmission, a common format is 7 data bits, an even parity bit, and one or two stop bits. That format accommodates all the 7-bit ASCII characters in an 8-bit byte. Other formats are possible; 8 bits of data plus a parity bit can convey all 8-bit byte values.

In serial communication contexts, parity is usually generated and checked by interface hardware (such as a UART) and, on reception, the result made available to a processor such as the CPU (and so too, for instance, the operating system) via a status bit in a hardware register in the interface hardware. Recovery from the error is usually done by retransmitting the data, the details of which are usually handled by software (such as the operating system I/O routines).

When the total number of transmitted bits, including the parity bit, is even, odd parity has the advantage that both all-zeros and all-ones patterns are detected as errors. If the total number of bits is odd, only one of the patterns is detected as an error, and the choice can be made based on what the more common error is expected to be.

Parity data is used by RAID arrays (redundant array of independent/inexpensive disks) to achieve redundancy. If a drive in the array fails, remaining data on the other drives can be combined with the parity data (using the Boolean XOR function) to reconstruct the missing data.

Should any of the three drives fail, the contents of the failed drive can be reconstructed on a replacement drive by subjecting the data from the remaining drives to the same XOR operation. If Drive 2 were to fail, its data could be rebuilt using the XOR results of the contents of the two remaining drives, Drive 1 and Drive 3:

A parity track was present on the first magnetic-tape data storage in 1951. Parity in this form, applied across multiple parallel signals, is known as a transverse redundancy check. This can be combined with parity computed over multiple bits sent on a single signal, a longitudinal redundancy check. In a parallel bus, there is one longitudinal redundancy check bit per parallel signal.

Parity was also used on at least some paper-tape (punched tape) data entry systems (which preceded magnetic-tape systems). On the systems sold by British company ICL (formerly ICT) the 1-inch-wide (25 mm) paper tape had 8 hole positions running across it, with the 8th being for parity. 7 positions were used for the data, e.g., 7-bit ASCII. The 8th position had a hole punched in it depending on the number of data holes punched.

Go to the System Settings and under the System section, hit Details. You will get every detail including your OS, your processor as well as the fact whether the system is running a 64-bit or a 32-bit version.

Open the Ubuntu Software Center and search for lib32. If that turns up any results, you are on a 64-bit install (the results are compatibility libraries for running 32-bit applications on a 64-bit install).

As far as I can remember, it is possible to install x86_64 kernel on a 32-bit system. As a few wrote here, you should look what libraries you have/what packages you have installed on your system. So the safest way to see is to check if you have /lib64 and if it is a symlink to /lib.

Another possible way is to check what packages you have downloaded in /var/cache/apt/archive. If they contain _amd64.deb, it is a 64-bit system, that is, if you have installed packages and have not cleared your cache.

Have a look at your Software Sources in Synaptic or Software Centre. If you haven't deleted your original source eg cdrom, it will (?) indicate the architecture. It's a GUI but it won't say '32bit' nor '64bit'.

Do you feel that my 32 bits environment should be called 32 bits (I believe so) or 64 bits (after all, it does run inside a 64 bits kernel). In that environment uname -m says i686 and all libraries and executables and processes are 32 bits.

I'm attempting to use bit-slice design, to implement a circuit which checks if an n-bit binary number A has an even number of 1's in its binary representation. I've decided that the circuit should produce an output of 0 if the number of 1's is odd, or 1 otherwise.

I'm currently fixated on one scenerio where the bit slice communicates the sum of the previous bits, a(i-1), with the current bit, a(i), all by ignoring the carry bit. It will transmit this sum to the next bit slice. Essentially , if a N-bit binary number is even, the final output sum will be 0, in which case I would invert the last sum bit. I'm not totally convinced on my approach, is there a better approach?

I have one AXI module. from upper side master is doing transaction W/R. for master data bus width is 256bits. transaction comes into module and module split that into 2.> bcoz lower side are two 128 bits databus width slaves. upperbits of data bus WDATA[255:128] goes to slave 1 and lowerbits of data bus WDATA[127:0] goes to slave 2. same for WSTRB[32:16] connected to slave 1 & WSTRB[15:0] connected to slave 2.

But in my unit level testing there are 3 protocol checkers. 1 for master and 2 for slave 1& 2. When master initiates the transaction it does not throw any error. but for slave it is throwing error : Write strobes must only be asserted for the correct byte lanes as determined from start address, transfer size and beat number.

Question: how should wstrb & awaddr & awsize & awlen & awburst work for slave 1 and slave 2. as they are half the data bus width.

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