There are by sure a lot of possibilities in the well know verification tools to
check the GDS file against their associated schematics. But I think the golden
way is already predetermined by the most-known/used layout editor. If you insert
a pin a rectangular area will be drawn with additional (hidden) properties.
These properties (or at least one) can be transfered to the GDS2-stream if you
want. If you do not attach the information the checker tool will not recognize
the pin name of the again streamed-in GDS2-file anymore -- LVS is not clean!.
Attaching properties to geometric shapes is of course not standardized but I
assume since this is the way done by the king of layout-editors 80% of the
design- and layout-engineers are familiar with this kind of work-flow. However,
I didn't found another way to keep the pin-information in the GDS-file when
using the standard stream-out procedure..
The way you suggested could be very possible if the fab supports this and
defines some specific rules in the checker tools. It would be great to hear
about the experience of other ASIC designers. I'm always open for new ways to
get things to work ;)
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