Top Gun Hard Lock - RELOADED PC Hack Activation Code
Cherrie Patete
In Chrome for desktop I have options in the dev tools to disable cache completely when dev tools are opened and I have the options to manually do a hard reload when long clicking on the reload button (with dev tools open).
Is there any such technique for Chrome for Android? I didn't find any setting.What can I do when I want to force the browser to download some javascript or css file instead of using a cached one when developing?
This must be done first, and you cannot re-open Chrome until you finish these steps. There are several ways to force stop. Most home launchers will let you get to "App info" by holding down your finger on the chrome icon and selecting an "i" icon. Alternately, you may be able to go to Android settings and simply search for "Chrome".
Additionally, I found a site that makes it easy to test if you've cleared your cache: -test/
I am in no way affiliated with it. Note that the method to clear the cache mentioned on that site is in fact outdated and no longer valid.
Recent versions of Chrome cache very aggressively. Even cache-busting techniques such as " =datecode" stopped working. You must clear the cache or launch an incognito window every time (and make sure data-saver is off).
This trick can refresh the CSS file, at least in Android's blue-globe-iconed default browser (but quite likely its twin, the official Chrome browser, too, and whatever other browsers we encounter on "smart"phones with their trend of aggressive caching).
At first I tried some of the fairly simple solutions shared here, but without success (for example clearing the recent history of the specific site, but not months and months of it). My latest CSS would however not be applied apon refresh. And that even though I had already employed the version-number-trick in the CSS file-call in the head section of the html which had helped me avoid these pesky aggressive cachings in the past. (example: link rel="stylesheet" href="style.css?v=001" where you upgrade this pseudo-version number every time you make a change to a CSS file, e.g. 001, 002, 003, 004... (should be done in every html file of the site))
This time (August 2019) the CSS file version number update no longer sufficed, nor did some of the simpler measures mentioned here work for me, or I couldn't even find access to some of them (on a borrowed android phone).
I made a copy of the site's index.html file giving it a different name (indexcopy.html), uploaded it, browsed to it on the Android device, then browsed back to the original page, refreshed it (with the refresh button left of the address bar), and voil: This time the refresh of index.html finally worked.
Explanation: The latest CSS file version was now finally applied on Android when refreshing the html page in question because the cached copy of the CSS file had now been updated when the CSS file was called from a differently named temporary html page that did not exist anywhere in the browser history and that I could delete again afterwards. The aggressive caching apparently ignored the CSS URL and went instead by the HTML URL, even though it was the CSS file that needed to be updated in the cache.
I've struggled with this for a CSS file that wouldn't refresh. But you can type the name of the CSS file itself into the address bar and refresh that. After that it's fine. Chrome on Android 8. Obviously that would be tiresome if you had more than a couple of files involved.
Now I have tested all server side and Android phone tricks above. Some might work for a day, but then suddenly nothing works.Does Android somehow compare the pages to their own server cache and follow some Google decisions, where and when use cache and when not ?
What doesn't work i100% of the time is an asynchronous "soft" reboot. This happens when the ARM resets the DSP and code is reloaded across the PCIe bus and the DSP restarted. Are there special steps required to reset the DSP to it's powered down state.
Based on my experience with other devices, I would suggest that before a DSP reboot the ARM issues some kind of "notice" to the DSP. The DSP would react by disabling any associated EDMA/McASP operations that are on-going and falling into a spin-loop to wait to be rebooted. The goal would be to avoid resetting the DSP while there's a memory transaction "in flight". If the DSP can stop its activity and just spin, I think the issues will go away.
But, in Linux, when a soft reboot is performed, the driver is not unloaded by the operating system, so there is not a clean shutdown. On the DSP side we capture the PCIe RESET event via a GPIO interrupt and then do a McASP (and EDMA) shutdown, but it is possible there could an EDMA PCIe bus-mastering transaction underway at the time of the PCIe RESET. Are there any registers we can look in to confirm a PCIe transaction error? And, is there a recovery mechanism?
Andrew Elder said:But, in Linux, when a soft reboot is performed, the driver is not unloaded by the operating system, so there is not a clean shutdown. On the DSP side we capture the PCIe RESET event via a GPIO interrupt and then do a McASP (and EDMA) shutdown, but it is possible there could an EDMA PCIe bus-mastering transaction underway at the time of the PCIe RESET. Are there any registers we can look in to confirm a PCIe transaction error? And, is there a recovery mechanism?
I don't quite understand the scenario. When you say a "soft reboot" are you referring to rebooting the entire chip, e.g. "reboot" command from Linux? Even in that case, I would have thought some type of hardware reset would be invoked under the hood as part of the reboot which would clear out any kind of pending errors, etc. Are you seeing an issue? Is the issue perhaps on the other side of the PCIe bus, i.e. do we put the other device into a bad state due to a partially completed transaction?
Important note - the PCIe reset line is not connected to the DM8147 reset pin because on many PCs the PCIe configuration registers cannot be loaded with the correct Hardware IDs (PCI VEN and SUBSYS) fast enough. ie, the time between when the PCIe reset linee going high and BIOS scanning the PCIe bus is faster than uboot can configure the PCIe Hardware IDs. So, for this reason, the PCIe reset line is wired to a GPIO pin and the DSP and ARM both "watch" for the PCIe reset line going low.
Sorry, I'm still confused! Was your initial note about "Linux soft reboot" referring to "Host PC reboot" or to "DM8147 reboot"? Initially I thought you meant the DM8147, but now I think you're referring to the PC. Is that correct? So your concern is that when you reboot the PC there might be some kind of "in flight" PCI transaction that causes issues? I don't know precisely how that's handled on this device. I would expect that a pluggable interface like PCIe has various timeouts and other error conditions to handle this sort of issue (though I'm admittedly not an authority on PCIe!).
Brad Griffis said:Sorry, I'm still confused! Was your initial note about "Linux soft reboot" referring to "Host PC reboot" or to "DM8147 reboot"? Initially I thought you meant the DM8147, but now I think you're referring to the PC. Is that correct? So your concern is that when you reboot the PC there might be some kind of "in flight" PCI transaction that causes issues? I don't know precisely how that's handled on this device. I would expect that a pluggable interface like PCIe has various timeouts and other error conditions to handle this sort of issue (though I'm admittedly not an authority on PCIe!).
Related to this whole topic, are you aware that you can reset the entire chip via software by using the PRM_RSTCTRL register? Maybe I'm headed the wrong direction here, but when you "see" that the Host PC is rebooting would it make sense to reboot yourself too? That would definitely clear out any errors that are pending!
Brad Griffis said:Related to this whole topic, are you aware that you can reset the entire chip via software by using the PRM_RSTCTRL register? Maybe I'm headed the wrong direction here, but when you "see" that the Host PC is rebooting would it make sense to reboot yourself too? That would definitely clear out any errors that are pending!
I have discussed this option internally and concluded that using a write to PRM_RSTCTRL to do a software reset of the DM8147 would result in the same "race" between uboot PCIe configuration and the host Linux PC BIOS reading back the PCIe configuration.
Andrew Elder said:I have discussed this option internally and concluded that using a write to PRM_RSTCTRL to do a software reset of the DM8147 would result in the same "race" between uboot PCIe configuration and the host Linux PC BIOS reading back the PCIe configuration.
It sounds like you made some changes with respect to the DSP shutdown/reload process that had a major impact. Are you still having issues? Just less regularly perhaps? Please refresh me on the current state of this issue in terms of what sort of symptoms you're seeing, how often, etc.
Yes, still having the issue. Manual driver unload/reload from Linux (no reboot) that resets the DSP and reloads DSP code works 100% reliably. Host Linux PC "soft" reboot (ie not a "hard" power cycle) that asserts PCIe RESET at some asynchronous time will run 100 times correctly and then fail. After the failure, the recovery requires a power cycle of the host Linux PC.
I am Andrew's colleague. Issuing a chip wide reset would make that issue go away but won't help us unfortunately because if we did that the endpoint would no longer be enumerated by the the root complex. We have verified that EDMA Transfer controller errstat and errdet register are clear right before the DSP is taken our of reset on a "bad boot run" i.e. the DSP locks up. The DSP has some exception flags and a buserr register but they are all in the DSP's internal RAM and thus not visible from the ARM. Connecting the emulator after the fact to inspect the state of the DSP has failed in the past for us because link fails repetedly and if/when it finally suceed the DSP has been reset by the connection process.
b1e95dc632