8255 Datasheet Download Upgrade
Janet Denzel
Well, OK - but there are three 74ls32's in the immediate vicinity (and a bunch more in the "north" part of the MB)! I tried to look at the service manual for the STROBE, but couldn't identify it - and the inner workings of the memory mapper hasn't opened up to me enough to completely understand what I am doing .... :evil:
p.s. I have to mention, that the "new old stock" I was supposedly ordering, seems to be used chips - bent and even dirty chip legs, and mixed batch numbers. But I ordered 20 - which means I have some extra - and I tested them and enough of them seemingly work (well, one didn't, and ones leg broke loose suddenly even before I tested it). In hindsight, maybe I should have gotten a 512kb SRAM and put together an instruction for using those chips, as I noticed there is some SRAM upgrade instructions on the page for 256kb which may even be enough for me to adapt the upgrade to 512 kb. I may do that later, especially if these chips turn out to be unstable in use.
In hindsight, maybe I should have gotten a 512kb SRAM and put together an instruction for using those chips, as I noticed there is some SRAM upgrade instructions on the page for 256kb which may even be enough for me to adapt the upgrade to 512 kb. I may do that later, especially if these chips turn out to be unstable in use.
I'd only consider using DRAM chips if you want a 4 MB expansion. Or you want 2 MB and don't want to stack SRAM chips 4 high. Or want 1 MB, and don't want to re-purpose a ROM socket to connect one or more SRAM chips.
The problem here is I do not want to guess - I want to be sure before I start soldering, since if the thing is not built properly in the first place, it will be impossible for me to troubleshoot. I want to be in the stage, where troubleshooting = re-checking all connections with multimeter.
I can see the rationale here. There's just the problem of lack of ready-made instructions - this is why I ordered the 4464 chips since there are some instructions available for using them. Using a more modern chip, might be simpler for someone adept with electronics, which I am not.
I should note here, that I do not work with electronics or anything of the kind for my daytime job. This is just a hobby for me (one of many, and I do other things than electronics in my free time!). In practice, when I see things like "STROBE signal" I go to Wikipedia and try to figure out what the h*** does it mean .
That being said, maybe with the help of this forum, a building guide for dummies (i.e. buy these parts, connect that pin to here and that one here) for memory expansion with newer chips could be made?
Also, no-one (aside for zPasis guesswork) has jet answered the original question: what is the STROBE signal? It must be called something else in SM? If zPasi is right, according to the SM, the STROBE is actually CAS2/E - and I believe that may actually make sense, since I think I've seen that in S3527 SM for the RAM slot selection - need to check that document, too. So the 74LS39 does RAM page(?) selection with the help of the 670, if CAS2/E is high? (This is probably clear as peaches for someone, but not for me )
I'm really starting to suspect that the 512kb instruction has a small but detrimental error in the schematic! Can someone who has build this (or has definite knowledge about the memory mapper) confirm this? It is certainly possible I've misunderstood something! Also, some of the documentation I've been reading is in Dutch (or some other language)
The error: I believe STROBE is indeed CAS2/E and should be connected to pins 1,15 of 74ls139, and pins 2 & 14 should be connected to pin 9 of the added 670 - and consequently 125 pin 5 (in the schematic these are swapped!). According to 139 datasheet, pin 1 is E1 and pin15 E2. It makes no sense to connect CAS2/E anywhere else? This would be in line with other memory mapper instructions I can find, and also the circuit just makes more sense to me this way...
Think about it. Both documents are about (in addition to adding the DRAMs themselves) the same thing: extending the memory mappers address range. The only difference should be that the 512K version requires one address line more. So of course they refer to the same 32 chip, which is IC111.
EDIT: Also, the error I've described is something easy to slip by - if there indeed is an error. Depending on the software used to draw the schematic, it could just be made with a single unintentional "click+drag" of 3mm, since it's actually just one connection in the schematic... and an experts brain may "fix" this error when he/she sees it and go unnoticed...
I think I will wait for more comments. There's bound to be someone who knows. Of course, I could just test which way the LS139 should be wired up, and which way it works, but I believe it is better wait for some answers than to try based on guesswork.
Also, I've already designed my workflow so that I can easily revert the changes. There's several reasons for it: I'm definitely not sure about the 4464 I've bought, so it is nice to be able to return using the original chips - or make an upgrade with some SRAM, provided I can find / gather enough information / knowledge to put together clear enough schematics for me to follow =)
In an MSX memory mapper, 74LS670 chips are used to generate the missing (above 16 bit) address lines. Well, actually more, because the memory is split to smaller parts (pages) than 64K. So, when software asks for a different page, a page number is stored in the 74LS670 which remembers the value. That is used as part of the address, when accessing the memory. Maybe this little piece of info helps to understand those circuits a little bit.
And, there are many ways to build a mapper, so it may not always be important which line is connected to which pin. For example, if some pin is connected between different pins on 670 chip and a DRAM chip, or even between different chips, it may still work. It doesn't matter which byte or page is where, so long they all have different addresses that don't overlap.
For hardware builders/modders, that's the only correct approach: understand first, THEN build. Not follow some dumb list of "cut here, connect that, ..." etc. If you don't know how [what you're building] works, then you can't fix it in case of problems. If you do understand how it works, then it is -relatively- easy to fix / work around problems, swap some pins, extend circuit a bit further, etc.
But with a memory mapper, A14 and A15 are used as 'selectors', which choose a register (of which there are 4), whose contents decides which 16KB block within the mapper is addressed. Contents of these "mapper registers" is what the programmer wrote (and STUPID programmers also read) to I/O ports FC..FFh. This re-directing of memory blocks is called "mapping", thus the name memory mapper.
It gets more complicated: quite a few crappy software exists that also reads these registers. To keep that software working, read-back of the registers is provided. Note that this is NOT an absolute 'must' ! A mapper where the registers can only be written but not read, should still be considered a properly working mapper. It's just that some (crappy) software has problems with that.
Indeed it looks like that 1st mentioned circuit has a mistake in it. But know that decoders like the '139 can often be (ab)used in different ways to achieve the same goal. So what looks like a mistake can be just a different way to obtain the required signals (I'm too lazy to check). Maybe it was done some time to swap some pins & make pcb layout easier, and others just copied that. Who knows.
With DRAMs, all those address line go into multiplexers (IC146/147) and you get "multiplexed address lines" (L0..L7 in the service manual). Basically each of those is two A.. lines in one ("MUX" signal indicates which). Then you have to deal with DRAM refresh. Control signal timing is also much more complicated than for SRAMs.
But don't stare yourself blind on all those mapper circuits! There's many ways that lead to Rome. For example in a 512 KB mapper of my own, I used a programmable logic device (CPLD) to do all that decode-I/O-ports-'670-register stuff. Looks very different, but operation principles & end result is the same.
I'm using as LS245 IC to connect 4 LEDs. The CS, RESET pins are connected to GND.I'm trying to use Port B to send data to switch ON/OFF individual LEDS. My code just sets control register to I/O mode, and port B is set as OUTPUT. Any pointers as to what can be wrong?
However, the Arduino does not have an external bus, so you are forced to emulate that bus by bit-banging individual I/O pins, which is slow and painful. Your code needs to generate pulses on the RD, WR, and CS pins, and it isn't currently doing that. You need to take a closer look at the timing diagrams in the 8255 datasheet.
All of these are almost identical in their operation. It is possible to detect each version by writing and then reading from the ppi control i/o port. Each can give a different pattern of values that are read back.
The 8255 PPI chip is a general purpose input/output IC. This document will describe its role in the Amstrad CPC, CPC+ and KC compact systems. To understand its full functions please read the datasheet.
In some of these modes, port C is used as a control/status port for port A or B. It can be used to confirm when data transfer may take place, and reflect any other flags. The 8255 PPI is therefore supplied with the added option for the user to set or reset any individual bits in port C.
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