GSoC project idea related to IBERT clone using LiteX

[Harsh Gugale]

Hello All,

I am a senior student at IIT (BHU), Varanasi and am pursuing a bachelors degree in Electronics Engineering. I want to contribute to the project idea on IBERT clone using LiteX.

I have used IBERT logicore by Xilinx in an internship before for multi-GBPS testing of an equalizer IC. I did some background research on the project, and some preliminary questions are as follows:

1) I started with Tim's talk in the linux.conf.au last January where he explains how python could be used to speed up design cycle. It was an excellent introduction. I wanted to understand how can we be sure that performance {P, L, A} of the design 'on FPGA' generated by python is at par with that of the Verilog code written alone. Actually, I have seen many people using MATLAB toolkits etc to code, but I never used those just because I was not sure about the hardware optimizations.

2) As I understand it, my job would be to design the python based GUI (I'll take the Xilinx logicore as an example.), the sequence generator and sequence checker (I assume these are simple LFSR based random number generator and checker where various parameters are set through GUI) blocks and as is outlined in the presentation, Wishbone Bus, WB2CSR bridge, and the CSR bus are available with MIGEN + MISOC package.

3) I have some doubts regarding the wrapper part which has been described. I did not understand what tool will enable us to change control parameters such as output swing or pre/post emphasis etc. Can Litescope be somehow used?

4) I do not possess any high-speed transceiver based FPGA, but I would like to spend some to procure an economical one. Any suggestions in this regard? 

Thank you for the help!

Regards,

Harsh 

[Rohit Kumar Singh]

Hello Harsh,

To answer your questions.

1) I started with Tim's talk in the linux.conf.au last January where he explains how python could be used to speed up design cycle. It was an excellent introduction. I wanted to understand how can we be sure that performance {P, L, A} of the design 'on FPGA' generated by python is at par with that of the Verilog code written alone. Actually, I have seen many people using MATLAB toolkits etc to code, but I never used those just because I was not sure about the hardware optimizations.

 

Litex/Migen is not an High Level Synthesis (HLS) framework. What we write in Python follows a slightly strict subset of Verilog coding rules, and the verilog code generated is exactly equivalent to a code manually written in Verilog. The advantage with Litex/Migen is that we can leverage Python to make designing hardware much more flexible. 

 

2) As I understand it, my job would be to design the python based GUI (I'll take the Xilinx logicore as an example.), the sequence generator and sequence checker (I assume these are simple LFSR based random number generator and checker where various parameters are set through GUI) blocks and as is outlined in the presentation, Wishbone Bus, WB2CSR bridge, and the CSR bus are available with MIGEN + MISOC package

For some reason, your image wasn't visible to me. Xilinx Transceivers have inbuilt PRBS (PRBS-7, 15, 23 and 31) generation and checking capability. Additionally, they also have Eye Diagram Scan hardware inbuilt. Main work from your side will involve instantiating transceivers correctly, and use DRP ports on the transceivers to control it.

 

3) I have some doubts regarding the wrapper part which has been described. I did not understand what tool will enable us to change control parameters such as output swing or pre/post emphasis etc. Can Litescope be somehow used?

You would need to use DRP ports to control these. I don't know whether Litescope can be used for this or not. mithro or _florent_ on #timvideos@freenode IRC channel might be able to answer that.

4) I do not possess any high-speed transceiver based FPGA, but I would like to spend some to procure an economical one. Any suggestions in this regard? 

I think you can do some research on this and come up with boards with high-speed transceivers. Then, we can check which ones are best suited. 

Rohit

[Florent Kermarrec]

Hello Harsh,

the idea with the project is to have a clone of what can be done with the IBERT Xilinx tools:

- 1) configure transceiver TX/RX parameters (electrical, post/pre emphasis, etc...)

- 2) configure transceiver TX to emit PRBS/ RX to receive check PRBS (PRBS-7, 15, 23, 31).

- 3) being able to recover the eye diagram for the RX.

For the gateware part, the module should just use CSR (no need for Litescope). With CSRs, you will be able to control and read values inside the module.

This repo should provide you the basis for this project :  https://github.com/enjoy-digital/transceiver_test

It would be nice to be able to easily generate a specific test design with multiple instance of the module to test transceivers of an fpga board.

For the software, you could probably use the existing python code to control registers and then add a gui on top that that would be similar what IBERT tool provides.

Regards,

Florent