GSOC project ideas related to Create a litescope based "Integrated Bit Error Ratio Tester" (iBERT) clone .

[Akhil Singh]

Hello All,

PFA the verilog code for synchronous FIFO coded by me.

I am a 3rd year dual degree student at IIIT , Hyderabad.I want to contribute to the project on IBERT clone using LiteX.

So,basically i have thought of some ideas to do this project which are:

1. The sub blocks needed to implement this project will be pattern generator, error checker, transceiver block, error logger and user interface.

2. Flow will be :

    -  First there will be PRBS generator.

    -  Then there will be error checker.

    -  Then Error logger.

    -  The error logger monitors and records the events to FIFO.

    -   The FIFO will communicate with the external IO interface.

3. Also i have access to high speed FPGA like Spartan 6 LXT.

Please provide the feedback on my ideas about the project and  the FIFO code (attached in mail).

Regards,

Akhil Singh