Standalone VCD to TIM converter

[Ed Carstens]

Is there an easy way to do a VCD to TIM conversion as part of a (batch mode) script?

[Dan Fabrizio]

Hi Ed,

I quickly created and tested the following script.

It can be modified to make vcd_dir and vcd_file command line arguments to be more versatile.

Dan 

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import os

from ta_py_lib.ta.app import *

from ta_py_lib.td.logic import *

from ta_py_lib.td.commands import *

from org.dmad.ta import VcdFileIO

vcd_dir = '/Users/danf/Projects/vcd_test_files'

vcd_file = 'it_fpga_tb_blk_pci_cycle.vcd'

fname, fext = os.path.splitext(vcd_file)

tim_file = fname + '.tim'

td = new_timing_diagram(taApp)

vcd = VcdFileIO(td,vcd_file,vcd_dir,'read')

taApp.fileSaveAs(dir, tim_file)

On Wed, May 27, 2015 at 5:30 PM, 'Ed Carstens' via TimingAnalyzer <timinga...@googlegroups.com> wrote:

Is there an easy way to do a VCD to TIM conversion as part of a (batch mode) script?

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Dan Fabrizio
The TimingAnalyzer
www.timing-diagrams.com

[Ed Carstens]

Thanks, Dan, but is there a way to do this in say a csh script in Linux?  Currently, I start JVM with:

java -jar jlib/jython.jar

This brings up the GUI. Then I open the VCD file using the GUI. I can run your script from the GUI, but it doesn't run as a Python script outside of the JVM. If I try, it gives the following error:

ImportError: No module named org.dmad.ta.logic

-Ed

[Dan Fabrizio]

Hi Ed,

Since the TimingAnalyzer uses Jython which runs on the java virtual machine,  it won't work directly from a csh script.

But you can do something like:

Put the script below at the end of a copy of the start_app.py and call it something like vcd2tim.py

Change vcd_dir and vcd_file to command line arguments and do something like.

java -jar jlib/jython.jar vcd2tim.py  'vcd_dir' 'vcd_filename'

I will test this script idea soon.

Dan

[Ed Carstens]

Thanks, Dan. I got this working now. This allows me to better automate a flow that converts VCD to TIM and does some additional custom modifications before I use the TA GUI to make final modifications. I'm using this to provide better documentation of simulation waveforms.

[Dan Fabrizio]

Hi Ed,

Sure.  No problem.  I think a good script would be to automatically parse a verilog or vhdl module and create the timing diagram generator source. Then the only thing you would have to do is run the script and include the generator module in your simulations.

I also fixed a few other VCD related issues and released a new version, beta0.984. 

Thanks, Dan