Hi Ed,
I fixed the first problem you reported in the previous message. The last value time in the vcd file was being used for the timing diagram end time. This caused the problem so I made the end time greater than the last value change time.
I'm working on this reported problem now and should have it fixed soon. These problems you are finding are a result of major changes made to the timing engine in the program in beta 0.980 which increased the time accuracy to femtoSeconds. This was needed for true logic simulations which I"m adding now so there will be 2 modes of operation, simulation or edit mode, in an upcoming version beta 0.990.
I expected some problems considering the extent of the changes made but don't have regression tests in place to catch issues when changes are made so I do as much manual testing as possible and hope to get feedback from beta users like you. I'm adding unit regression tests now as well which will help find issues before new versions are released
Thanks for you feedback,
Dan