Announcement: new beta version b0.984

[dan_fabrizio]

Hi All,

I have released a couple of new versions recently to fix issues mainly related to VCD file parsing.  

Please try the latest version, beta 0.984,  when you get a chance.

• Fixed VCD bus size values not the correct length.
• Fixed VCD analog signal drawing routine to use new time engine.
• Fixed VCD analog example sine_waves.vcd
• Fixed VCD file time scale - error shown when label not centered.
• Updated verilog app note source files to use new scripting API.

As always,  questions and feedback are welcome.

Thanks, Dan