Launchpad I2C signal byte RX/TX problem.

[Shiwei Luan]

I am new to MSP-EXP430G2 and confused on I2C demo codes.

What I did is just import demo codes from CCSV5.5 for I2C Slave and Master as following. It's supposed to transmitter one byte to master. My questions are: 

1) How does master set R/W with address? In this case, slave address is 0x38, so the last bit is 0. So master will write byte to slave not read from slave?

2) When slave receive first address package from master, how does code go into interrupt? As far as I know, UCSTTIFG will be set if address matches. But in this slave codes, it will step into USCIAB0RX_VECTOR, then USCIAB0TX_VECTOR. Which register or bit can tell codes to go into interrupt? (Such as voltage change on GPIO will generate interrupt).

Thank you, pros.

The following are Slave codes:

#include <msp430.h>

unsigned char TXData;

int main(void)

{

      WDTCTL = WDTPW + WDTHOLD;                 // Stop WDT

      P1DIR |= BIT0;                            // P1.0 output

      P1REN = 0x00;

      P1SEL |= BIT6 + BIT7;                     // Assign I2C pins to USCI_B0

      P1SEL2|= BIT6 + BIT7;                     // Assign I2C pins to USCI_B0

  

      UCB0CTL1 |= UCSWRST;                      // Enable SW reset

      UCB0CTL0 = UCMODE_3 + UCSYNC;             // I2C Slave, synchronous mode

      UCB0I2COA = 0x48;                         // Own Address is 048h

      UCB0CTL1 &= ~UCSWRST;                     // Clear SW reset, resume operation

      UCB0I2CIE |= UCSTTIE;                     // Enable STT interrupt

      IE2 |= UCB0TXIE;                          // Enable TX interrupt

      TXData = 0xff;                            // Used to hold TX data

      while (1)

      {

        __bis_SR_register(CPUOFF + GIE);        // Enter LPM0 w/ interrupts

      }

}

 // USCI_B0 Data ISR

#pragma vector = USCIAB0TX_VECTOR

__interrupt void USCIAB0TX_ISR(void)

{

      UCB0TXBUF = TXData;                       // TX data

      __bic_SR_register_on_exit(CPUOFF);        // Exit LPM0

}

// USCI_B0 State ISR

#pragma vector = USCIAB0RX_VECTOR

__interrupt void USCIAB0RX_ISR(void)

{

      UCB0STAT &= ~UCSTTIFG;                    // Clear start condition int flag

      TXData++;                                 // Increment data

}

The following are Master codes:

#include <msp430.h>

unsigned char TXData;

int main(void)

{

      WDTCTL = WDTPW + WDTHOLD;                 // Stop WDT

      P1DIR |= BIT0;                            // P1.0 output

      P1REN = 0x00;

      P1SEL |= BIT6 + BIT7;                     // Assign I2C pins to USCI_B0

      P1SEL2|= BIT6 + BIT7;                     // Assign I2C pins to USCI_B0

  

      UCB0CTL1 |= UCSWRST;                      // Enable SW reset

      UCB0CTL0 = UCMODE_3 + UCSYNC;             // I2C Slave, synchronous mode

      UCB0I2COA = 0x48;                         // Own Address is 048h

      UCB0CTL1 &= ~UCSWRST;                     // Clear SW reset, resume operation

      UCB0I2CIE |= UCSTTIE;                     // Enable STT interrupt

      IE2 |= UCB0TXIE;                          // Enable TX interrupt

      TXData = 0xff;                            // Used to hold TX data

  while (1)

  {

        __bis_SR_register(CPUOFF + GIE);        // Enter LPM0 w/ interrupts

  }

}

// USCI_B0 Data ISR

#pragma vector = USCIAB0TX_VECTOR

__interrupt void USCIAB0TX_ISR(void)

{

      UCB0TXBUF = TXData;                       // TX data

      __bic_SR_register_on_exit(CPUOFF);        // Exit LPM0

}

// USCI_B0 State ISR

#pragma vector = USCIAB0RX_VECTOR

__interrupt void USCIAB0RX_ISR(void)

{

      UCB0STAT &= ~UCSTTIFG;                    // Clear start condition int flag

      TXData++;                                 // Increment data

}