arithmetic shift_reg design code

[Tuan]

module shift_reg(
data_in,
clk,
d,
data_out
);
// input
input [7:0] data_in;
input clk;
input d;
//output
output [7:0] data_out;
//reg
reg [7:0] data_out;
always @ (posedge clk)
begin
if (d)
data_out <= { data_in[7],data_in[5:0],1'b0 };// d=1 thi dich trai.
else
data_out <= { data_in[7],data_in[7:1]};// d= 0 thi dich phai
end
endmodule

[Anh Tuan Vu]

2011/11/7 Tuan <vangtr...@gmail.com>

--

Vũ Anh Tuấn