What is Cashe Memeory L1 & L2 Cashe Memory?

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=== CACHE ===
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Cache is a small fast SRAM type of memory. It prevents CPU slowdown,
which happens when the CPU has to wait on slower devices like RAM
memory and the hard drive. There are two levels of cache.

Level 1 or L1 cache is a small fast memory located on the same chip as
the CPU. When files are first requested by the CPU they are read into
the CPU from the hard drive and written into the L1 cache at the same
time. When the CPU needs data again it checks the L1 cache and if it
finds it there it gets it instantly. If not, it looks successively in
the L2 cache, RAM and finally the hard drive, each of which is a little
slower in delivering the data the CPU has requested.

If the CPU finds the data it wants in a cache it's called a 'hit' and
that's good. If it doesn't it's called a 'miss' which makes the CPU
wait a little longer to get the data or instruction it needs from one
of the other slower devices.

This little bit of time saved by cache hits may not seem significant,
but keep in mind that millions of accesses can be performed in a
second. Every cache hit shaves time off the data access. Every cache
miss adds time to the access. Cache misses lower performance and cache
hits raise it!

Because level 2 or L2 cache is located in chips on the motherboard or
on the board that holds the CPU it takes a little longer to access than
the L1 cache.

L2 cache is becoming more important as it grows in size and
performance. The L1 cache is very small because it is on the same chip
as the large CPU. Due to it's small size, chances are high that the CPU
won't find the data it needs there. An L1 cache miss causes the CPU to
look in the L2 cache for the data.

The long and short of all this - If the data the CPU needs is not found
in the L1 cache or L2 cache, the CPU must to wait to get it from the
RAM memory. And if it isn't in RAM, then the CPU goes on vacation for a
number of milliseconds, which is a long time in the CPU world, while
the data is retrieved from the hard drive.
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