Design for Test: Interview question on Stuck at fault

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Jun 18, 2025, 7:10:11 AMJun 18
to The Digital Electronics Blog

In Design for Testability (DFT), explain how a stuck-at-1 fault on the input of a 3-input AND gate affects the output behavior, and describe how you would design a test pattern to detect this fault in a scan-based test methodology.

Provide a specific test vector and explain why it ensures fault detection.

Karthik Ramanathan

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Jun 18, 2025, 7:13:51 AMJun 18
to The Digital Electronics Blog

A stuck-at-1 fault on input A of a 3-input AND gate makes A always 1, so the output depends only on B and C (output = B AND C).

To detect this, use test vector A=0, B=1, C=1; fault-free output is 0 (0 AND 1 AND 1), but faulty output is 1 (1 AND 1 AND 1).

In scan-based testing, shift in (0,1,1), capture the output, and shift out to observe the fault.

This ensures controllability and observability for detection.

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