Analog Electronics Jb Gupta Pdf Free Download
Avery Blaschko
Chirag is broadly interested in wide-band-gap (GaN, SiC) and ultra-wide-band-gap (GaOx, C) semiconductor materials and devices. These semiconductors alongside Silicon will provide solutions to emerging technological challenges in the areas of power electronics, communications, bio-electronics, and quantum applications. Specifically, his research focuses on how these semiconductors can be utilized to develop next-generation electronics (transistors, diodes, etc.) and optoelectronics (LEDs, Lasers, etc.) devices. His research will involve an in-depth understanding of semiconductor device physics and fabrication technology applied to develop novel device designs, fabrication techniques, electrical and material characterization, data analysis and repeat!
In this study, the authors propose a novel MgZnO/CdZnO Quadruple-Gate Field Effect Transistor (QG-FET). The analog/RF and linearity distortion performance of the proposed QG-FET has been analysed and compared with conventional AlGaN/GaN QG-FET having identical physical dimensions. The performance parameters including drain current (IDS), gate capacitance (Cgs), output-conductance (gd), transconductance (gm1), transconductance generation factor (TGF), intrinsic-gain (dB), cut-off frequency (fT), transconductance frequency product (TFP), first and second order derivatives of gm1 (i.e., gm2 and gm3), third order intermodulation distortion (IMD3), third order input intercept point (IIP3), and extrapolated input voltages (VIP2 and VIP3) have been calculated. The consequences of variations in physical parameters of proposed QG-FET viz., thickness of oxide layer (tox), channel length (CL), and doping concentration (Nd) on the analog/RF and linearity distortion parameters are analyzed and compared with conventional AlGaN/GaN QG-FET. It has been revealed that MgZnO/CdZnO QG-FET yields higher IDS, gm1, TGF, intrinsic gain (dB), fT, and TFP than conventional AlGaN/GaN QG-FET with respect to different values of tox, CL, and Nd.
The challenge of designing of high performance low-voltage and low-power analog circuits is increasing due to the scaling down of CMOS technology and the increasing demand for portable electronic equipments [1]. The speed of conventional analog integrated circuits is degrading on reducing the supply voltage for a given technology. To fulfill these requirements, the researchers are focusing on the development of new integrated circuits that have low voltage supply requirement, without any degradation in the performance.
One of the basic building blocks in analog signal processing circuits is voltage buffer, which is used to drive low-impedance loads (Figure 1(a)). The flipped voltage follower (FVF) [2] is a low-voltage operating buffer that can be used in different circuits in place of conventional voltage buffer very efficiently. A FVF circuit is shown in Figure 1(b).
Ramirez-Angulo et al. [3] have introduced an FVF which is based on FGMOS level shifter stage, shown in Figure 2. Due to its high swing and low voltage operation, the FGMOS-based FVF can be preferred over conventional FVF in many high-swing, low-power, and wideband analog integrated circuits.
In many analog circuits, it is required to drive the impedance by a voltage buffer like that in operational amplifiers. For low-power circuits, low-power voltage buffers are used as output stages. The FVF has overcome the drawbacks of conventional voltage buffers. It has low-power dissipation, large output signal swing, low settling time, and almost unity gain [2]. Moreover, class AB biasing can be employed to reduce power consumption without affecting the ability to drive large capacitive loads [14]. Figure 5 shows an output stage based on conventional FVF [15]. But a FVF will not work properly in class AB. Centurelli et al. [14] have developed an output stage which was based on FVF operating in class AB (Figure 6).
The paper has presented two new buffers that can be used as output stage in many analog and mixed-signal circuits. The circuit parameters of FVF-based output buffer and class AB output buffers are given in Tables 2 and 3, respectively.
In this paper, two new low-power low-voltage and wideband output stages based on FVF with floating gate level shifter have been proposed. The use of floating gate technology provides the advantages of low-power consumption and low-power supply requirement. Moreover it gives a significant improvement in the bandwidth of the systems and the ability of the buffers to drive heavy capacitive loads by decreasing the output impedance. The simulation results have shown that the proposed buffers display good characteristics when compared with the reported works achieved so far. These improved buffer structures can be useful as output stage in many analog signal processing applications.
Ayman Fayed received his B.Sc. degree in Electronics & Communications Engineering from Cairo University in 1998, and his M.Sc. and Ph.D. degrees in Electrical & Computer Engineering from The Ohio State University in 2000 and 2004, respectively. From 2000 to 2009, he held several technical positions in the area of analog, mixed-signal and power management integrated circuit design at Texas Instruments Inc., where he contributed to many product lines for wire-line, wireless, and multi-media devices. From 2000 to 2005, he was with the Connectivity Solutions Dept. at TI, where he worked on the development of analog frontends for high-speed wire-line transceivers such as USB, IEEE1394b, and HDMI, and on fully integrated switching/linear regulators and battery chargers for portable media players. From 2005 to 2009, he was a member of the technical staff with the wireless analog technology center at TI, where he worked on delta-sigma data converters for various wireless standards, and on the development of fully-integrated power management solutions for mixed-signal SoCs with multi-RF cores in nanometer CMOS. Dr. Fayed joined the Dept. of Electrical & Computer Engineering at Iowa State University in 2009, where he held the Northrop Grumman Assistant Professorship. He then joined the Dept. of Electrical & Computer Engineering at The Ohio State University in 2015, where he is currently a professor. He is the founder and director of the Power Management Research Lab (PMRL) and his current research interests include on-chip power supplies for dynamic energy distribution in VLSI systems, high-frequency switching regulators with on-chip and on-package passives for SoCs, low-noise power supplies and power supply modulators for analog and RF circuits, energy-harvesting circuits for power-restricted & remotely-deployed devices/systems, and analog/mixed-signal and power converter design in SiC and GaN technologies. He is currently the chair of the Analog Signal Processing Technical Committee of the IEEE CAS society, and a member of the Technical Program Committee of ISCAS, APEC, and the steering committee of MWSCAS. He has served previously as an associate editor for IEEE TCAS-I and TCAS-II and in the Technical Program Committee of RFIC. Dr. Fayed is the author/co-author of many publications in the field and holds 8 US patents. He is a recipient of the NSF CAREER Award in 2013, the 2015 Darlington Best Transactions Paper Award from the IEEE Circuits and System Society, and the 2021 IEEE Transactions on Power Electronics Second Place Prize Paper Award from the IEEE Power Electronics Society. He has also received the Best Associate Editor Award from IEEE TCAS-I in 2020, 2021 and 2022, and the 2022 IEEE CAS Society Outstanding Technical Committee Award. Dr. Fayed is a senior member of IEEE. LinkedIn Profile.
Robbie Milner received his B.Sc. degree in Electrical and Computer Engineering from The Ohio State University in May, 2022. He has worked as a process engineering intern for TTM Technologies in the summer of 2021, where he designed a robotic work cell to automate and increase efficiency of the factory line. He joined PMRL in January 2022 as an undergraduate research associate and is continuing towards his Ph.D. degree starting August, 2022. Robbie's research is focused on analog and power management IC design. LinkedIn Profile.
Hua Zhang received his B.Sc. and M.Sc. degrees in Electronics Engineering from Southeast University, Nanjing, China, in 2005 and 2008, respectively. From 2008 to 2017 he was an analog and mixed-signal IC design engineer at Qimonda (Suzhou, 2008-2009), EPC (Changshu, 2009-2011) and Diodes (Shanghai, 2011-2017). His industrial experience includes high speed ADCs, timing circuits, and low-power Primary Side Regulation AC-DC battery chargers/adapters. Hua joined PMRL in 2017 to pursue his Ph.D. His current research interests include wideband switching power modulators for RF applications and power converters in SiC technologies. Hua completed his Ph.D. degree in 2022. His thesis is entitled "Fully Integrated Switching Power Converters in Silicon Carbide Technology". Hua has accepted a senior analog and power management IC design engineer with Texas Instruments Inc. LinkedIn Profile.
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