在vcs7.1.2环境下,无法跑仿真,请求帮助

[duho...@sina.com]

我是 SystemVerilogAssertion应用指南的读者,在利用光盘中提供的代码做练习时,

发现跑不起来,怀疑是脚本的问题,改了后,还是跑不起来.周围也没有可以讨论的人,只能想你们请教了

 

source code

chapter1 /cond

使用原来的脚本的错误结果为:

./run: line 1: simv: command not found

 

改了脚本后:

脚本为:vcs  +sysvcs \
+define+ASSERT_ON+SVA \
-y $VCS_HOME/packages/sva \
+libext+.v \
+incdir+$VCS_HOME/packages/sva \
cond.v\

simv -l run.log -assert filter+success

报错的信息为:

*** Using loader /usr/ccs/bin/ld instead of cc ...
                         Chronologic VCS (TM)
              Version 7.1.1 -- Mon Mar 12 16:47:02 2007
               Copyright (c) 1991-2003 by Synopsys Inc.
                         ALL RIGHTS RESERVED

This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.

Parsing design file 'cond.v'
Error-[UST] Undefined system task
        Undefined System Task call to '$vcdpluson'
        "cond.v", 20: token is ';'
initial $vcdpluson();
                     ^
Error-[SE] Syntax error
        "cond.v", 73: token is '->'
        @(posedge clk) $fell(start) |-> (!start) throughout (##1 (!a&&!b) ##1 (c[->3]) ##1 (a&&b));
2 errors
CPU time: 1 seconds to compile
./run: line 8: simv: command not found

 

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[me.j...@gmail.com]

Pls try newer version VCS such 2005.06 or newer

Error-[UST] Undefined system task
Undefined System Task call to '$vcdpluson'
"cond.v", 20: token is ';'
initial $vcdpluson();
^

JJC : please add "-PP" in older version or "-debug_all" in newer
version

Error-[SE] Syntax error
"cond.v", 73: token is '->'
@(posedge clk) $fell(start) |-> (!start) throughout (##1 (!a&&!
b) ##1 (c[->3]) ##1 (a&&b));

JJC : please use newer version since vcs7.1.1 may not have SVA support
yet .

Good lucky !

On 3月12日, 下午4时50分, duhong...@sina.com wrote:
> 我是 SystemVerilogAssertion应用指南的读者,在利用光盘中提供的代码做练习时, 发现跑不起来,怀疑是脚本的问题,改了后,还是跑不起来.周围也没有可以讨论的人,只能想你们请教了 source code chapter1 /cond 使用原来的脚本的错误结果为: ./run: line 1: simv: command not found 改了脚本后: 脚本为:vcs +sysvcs \+define+ASSERT_ON+SVA \-y $VCS_HOME/packages/sva \+libext+.v \+incdir+$VCS_HOME/packages/sva \cond.v\ simv -l run.log -assert filter+success 报错的信息为: *** Using loader /usr/ccs/bin/ld instead of cc ... Chronologic VCS (TM) Version 7.1.1 -- Mon Mar 12 16:47:02 2007 Copyright (c) 1991-2003 by Synopsys Inc. ALL RIGHTS RESERVED This program is proprietary and confidential information of Synopsys Inc.and may be used and disclosed only as authorized in a license agreementcontrolling such use and disclosure. Parsing design file 'cond.v'Error-[UST] Undefined system task Undefined System Task call to '$vcdpluson' "cond.v", 20: token is ';'initial $vcdpluson(); ^Error-[SE] Syntax error "cond.v", 73: token is '->' @(posedge clk) $fell(start) |-> (!start) throughout (##1 (!a&&!b) ##1 (c[->3]) ##1 (a&&b));2 errorsCPU time: 1 seconds to compile./run: line 8: simv: command not found
>
> -------------------------------------------------------------------
> 大小单双 机会重重 10分钟就开奖 立即返奖(http://ad4.sina.com.cn/sina/limeng3/mail_zhuiyu/2007/mail_zhuiyu_2007...)
>
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