Altera De2 Board

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Ilona Brownson

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Aug 3, 2024, 4:43:30 PM8/3/24

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The purpose of the Altera DE1 Development and Education board is to provide the ideal vehicle for advanced design prototyping in the multimedia, storage, and networking.
It uses the state-of-the-art technology in both hardware and CAD tools to expose designers to a wide range of topics. The board offers a rich set of features that make it suitable for use in a laboratory environment for university and college courses, for a variety of design projects, as well as for the development of sophisticated digital systems. Altera provides a suite of supporting materials for the DE1 board, including tutorials, "ready-to-teach" laboratory exercises, and illustrative demonstrations. Link to Altera DE1

Terasic is the leading developer and provider for FPGA-based hardware & complex system solution. With twenty years of experience in developing high-end solutions for the industrial and FPGA system markets.

The Altera DE2-70 development and education board, equipped with almost 70,000 LEs of Altera Cyclone II 2C70, not only adopts the advantages of the Altera DE2 board such as the multimedia, storage, and networking interfaces but also has larger memory components than ever before. The board offers a rich set of features that make it suitable to be used in a laboratory environment for university and college courses, for a variety of design projects, as well as for the development of sophisticated digital systems. Altera provides a suite of supporting materials for the DE2-70 board, including tutorials, "ready-to-teach" laboratory exercises, and illustrative demonstrations.

Years ago (in 2004) my university got an Altera MAX-II devboard, but nobody used it. Now it's me who must teach students FPGA programming, but I still cannot get the board programmed. I faced the following issues, in order:

Okay, I found a computer with LPT, and installed modern Quartuas II 14.1 software on it. I was able to examine firmware from FPGA using ByteBlaster cable, but not to program it. Unfortunately, 14.1 supports EMP1270F256C5 chip only while my board has EMP1270F256C5ES (that stands for "engineering sample" which is kind of beta-version of the production chip); POF files for these chips are incompatible. Can I somehow install support for my old chip in modern Quartus?

Alternatively, and probably more sensibly, you could upgrade to a more modern device. There are for example many Cyclone V based dev kits that are pretty cheap, though I'll let you search for something.

If you are trying to teach FPGA based stuff, using an ancient device, especially one which is an engineering sample, is possibly not the best course of action - you'd spend more time battling bugs and glitches in the tools (if you can even get them set up) than you would teaching.

The package from seller also contains several sample .sof (SRAM Object File) files, which is a binary format used by the board programmer. I wanted to load them on the device, one needs to use Quartus Prime Programmer to do that, with the USB blaster connected between the computer and the board. The board obviously needs to be powered on by a separate micro USB cable.

Note: I had to adjust the pin type for nCEO: Use as regular I/O in Quartus as the pin was colliding with the LCD data 0 pin (P101) - you can set this in Device and Pin options or in the .qsf file as set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"

Although I had to buy a cheap PS/2 keyboard to test out this port, a sample VHDL file to display the scan code on the display showed weird output. The mapping to the display segments was incorrect in the sample file, so I fixed it and was able to see the scan code on the display: 29 is generated by the space bar.

Terasic DE10-Lite is a cost-effective Altera MAX 10 based FPGA board. The board utilizes the maximum capacity MAX 10 FPGA, which has around 50K logic elements(LEs) and on-die analog-to-digital converter (ADC). It features on-board USB-Blaster, SDRAM, accelerometer, VGA output, 2x20 GPIO expansion connector, and an Arduino UNO R3 expansion connector in a compact size. The kit provides the perfect system-level prototyping solution for industrial, automotive, consumer, and many other market applications.

3) a really good mini project would be to get that ADC working, using 100% your own code, not the stuff that comes with the board. You'll need to get and understand the data sheet for the ADC and to make a decent simulation testbench you will need to make a model of the ADC.

Description:

Low cost development board for the Altera EPM240T100C5 (MAXII) CPLD device. Using Altera's free design suite complex schematic or HDL designed can be easily created and downloaded into this development board (hardware programmer required, available here). An on board regulator allows and standard DC socket allows for convenient powering. There is also an on-board crystal to allow your designs to include clocks and other timing functions.

I have already tried out the " Freedom E300 Arty FPGA Dev Kit" from , but I still want to evaluate more cores. So is it possible for me to use these verilog files to generate a useable bitstream file for my FPGA? Could you write some guides on how to put the FPGA Eval Kits into different FPGA boards?

As far as I know, many low-end FPGA boards from Altera are cheaper than those from Xilinx. As a result, many students/beginners would choose Altera boards rather than Xilinx boards. I think such guides will make the risc-v community more popular.

I think the key point of putting SiFive Core IPs in Altera boards is replacing Xilinx primitives with Altera primitives, or replacing Xilinx IPs with Altera IPs. Besides we also have to change the constraint file for different hardware. Therefore, I think that you could tell users the Xilinx primitives and IPs you used for SiFive Core IPs, and the occupied LUTs/FFs/BRAMs/DSPs of particular SiFive Cores. In this way, users could evaluate the minimal FPGA boards they need.

Does sifive provide all sources(RTL, Constraint,non encrypted rtl, netlist) require to create xilinx vivado project from scratch.
as Developer may have custom in house developed xilinx FPGA Board or xilinx evaluation board. In such a scenario is it possible to reuse existing boards instead of sticking to boards supported/internally use by SiFive.

Altera programmable solutions enable system and semiconductor companies to rapidly and cost-effectively innovate, differentiate and win in their markets. Find out more about Altera's FPGA, CPLD and ASIC devices at www.altera.com.

The DE0 Development and Education board is designed in a compact size with all the essential tools for novice users to gain knowledge in areas of digital logic, computer organization and FPGAs. It is equipped with Altera Cyclone III 3C16 FPGA device, which offers 15,408 LEs. The board provides 346 user I/O pins, and is loaded with a rich set of features that makes it suitable to be used for advanced university and college courses, as well as the development of sophisticated digital systems. The DE0 combines the Altera low-power, low-cost, and high performance Cyclone III FPGA to control the various features of the DE0 Board. The DE0 Development Board includes software, reference designs, and accessories required to ensure the user simple access in evaluating their DE0 Board.

I am looking for a NIOS design that I can program on my Altera DE2-115 board (using Quartus II V14.0) on which I then run the "count binary" template that is part of the NIOS-Eclipse IDE. I am currently using a NIOS design that is part of one of the demo projects that come with the DE2-115 board (the USB device project), and with this NIOS design, I can see the counter counting on stout (via JTAGUART), but not on the board LEDs, 7-segment displays, or LCD display.

You can add PIO (Parallel I/O) megafunction to your QSYS and connect LEDs to NIOS this way. The value will be transferred to the FPGA pins and the LEDs will be turned on/off according calculation result. With a little modification of your C code and connection to the right FPGA pins (export interface from QSYS) it will work fine. For 7-segment display you need to write a bit more C code, to decode the value and turn on/off the needed segments of 7-segment elements. Unfortunatelly I am not familiar with this particular board and its LCD display.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.