SVUnit in UVM mode with module-based DUT

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Mar 6, 2019, 8:03:34 PM3/6/19

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Greetings all -

is it possible to use SVUnit in UVM mode with a DUT that's a Verilog module?

create_unit_test.pl and runSVUnit.pl with "-uvm" arguments seem to expect the DUT to be derived from uvm_component.

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