Testing VHDL Modules
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jarick cammarato
Aug 31, 2016, 9:05:19 PM8/31/16
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Hey all. I am looking to get into unit testing and am interested in svunit over something like vunit because it aligns with my employers desire to move more toward SV and UVM test benches. I watched the verification academy videos and was impressed. Unfortunately for me all of our designs are VHDL. We have never done anything but VHDL design and TB so I have no experience with mixed language simulation. I haven't found anything about using svuint on vhdl designs. Does this mean it is not supported or is their some work around that I should generally be aware of?
neil johnson
Sep 6, 2016, 11:59:51 AM9/6/16
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hey jarick, I keep telling people that I'm close to supporting vhdl but then I never get to it. I'll try and make it different this time. what simulator are you using?
Tudor Timi
Sep 7, 2016, 7:56:43 AM9/7/16
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I don't see what you need to build to support VHDL. It all comes down to simulator support. If the simulator supports instantiating VHDL under SystemVerilog, than that's all you need. Of course you need to take care of port types at the language boundary (again, this depends on the simulator). Writing tests that toggle inputs and only make checks on the design's outputs should work the same, regardless of what language the DUT is written in.
At the same time, trying to write tests that check internal signals isn't going to be easy (i.e. stimulate something and expect some internal signal to toggle in a certain way). For Verilog designs you can just reach into the design and check signals, but for VHDL this might not be possible (since the VHDL standard doesn't allow hierarchical paths AFAIK). Some simulators allow this, while some might not.
At the same time, trying to write tests that check internal signals isn't going to be easy (i.e. stimulate something and expect some internal signal to toggle in a certain way). For Verilog designs you can just reach into the design and check signals, but for VHDL this might not be possible (since the VHDL standard doesn't allow hierarchical paths AFAIK). Some simulators allow this, while some might not.
neil johnson
Sep 8, 2016, 1:16:06 AM9/8/16
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I think you're right about vcs and incisive. seems you just specify vhdl files on the command line. not sure if there's a way around it but I added vcom to the questa flow for vhdl compile. the result is now users can specify a vhdl filelist with files/switches/etc using: runSVUnit -m <vhdl file list> <blah blah blah>
-neil
neil johnson
Sep 13, 2016, 5:10:25 PM9/13/16
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jarick, just a heads-up that I have at least 1 person vouching for the vhdl/verilog mixed signal svunit sim. seems to work with modelsim at least.
-neil
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