Failed to run simple unit test

[陳耘志]

Hi, I'm a new to both Verilog and SVUnit.

I try to run an unit test against a simple adder like this: http://codepad.org/wHl4TVdf

The test file looks like this: http://codepad.org/nByZGBNz

However, it fails.

Could someone give some insight?

Thanks a lot!!!

[neil johnson]

unit testing combinational logic can be tricky at first b/c of the timing. with the '<=' assignments and the immediate `FAIL_IF, the comb output doesn't have time to resolve in the simulator. a #0 before the `FAIL_IF should change that...

  `SVTEST(simple_add_test)
    data1_in <= 32'd10;
    data2_in <= 32'd01;
    #0 `FAIL_UNLESS(32'd11 === data_o);
  `SVTEST_END