VHDL UUT

[Mark Sankey]

Can I use SVUnit to support me in the writing of systemVerilog unit tests to verify a VHDL DUT?

[Simon Robidas]

Hello Mark,

Yes, you can. If you invoke runSVUnit -help, you'll see that there is a -m option for mixed language simulation.

Here is a wrapper makefile I use to run unit tests which include VHDL instantiations:

============================

SHELL    := /bin/bash

INCDIR   := -c +incdir+../ 

clean:

@rm -rfv work

@rm -fv .svunit.f

@rm -fv .testrunner.sv

@rm -fv .__testsuite.sv

@rm -fv *.log

@rm -fv transcript

ut:

runSVUnit -s questa $(INCDIR) -d SVUNIT -r '-do batch.do' -m vhdl-file-list.f 

===================================

I have a subdirectory under the dir where my DUT resides, which is why I set +incdir+../. So the DUT is one dir up from where I run SVUnit.

In batch.do I keep options I might need to pass to Questa, or any other pertinent TCL command.

The vhdl-file-list.f simply contains a list of vhdl files, including relative paths like so:

../../../file1.vhd

file2.vhd

Cheers,

Simon