Exploring Zynq Mpsoc

[Kristin Klodzinski]

Theexample lets you test the control algorithm by using a closed-loop system simulation. You can then generate HDL code for the control algorithm. It supports both quadrature encoder sensor-based and sensorless flux observer-based closed-loop motor control during simulation and hardware deployment.

The example includes a MATLAB project that provides the models and the reference design. Use the project with the HDL Workflow Advisor for bit stream generation and for running an external mode model to interact with the processor.

You can apply the techniques shown in this example to partition and deploy the controller algorithms. This image shows the generalized workflow from model simulation to deployment of the controller algorithm onto an embedded hardware board.

Simulate a system test bench to gain insight into the behavior of the controller algorithm design. Then explore the design to see how the algorithm is partitioned. The high rate portion of the algorithm is partitioned into a model that is configured for HDL code generation. The low rate portion of the algorithm is partitioned into a model that is configured for C code generation. Generate C and HDL code from these models and learn how you can integrate this code into your design.

After exploring C and HDL code (model) for the algorithm, use automated deployment of code into the reference frameworks for the processor and programmable logic. Then, execute a test on the deployed application, log the results, and compare them with the simulation results.

Because this example deploys a bitstream and ARM executable to the Xilinx Zynq hardware, you must set up the Xilinx Zynq hardware board before starting the example. To ensure that you have setup the environment correctly, follow and complete the Getting Started with Targeting Xilinx Zynq Platform (HDL Coder) example using your hardware configuration before starting this example. The figure shows the Hardware Board selection used in this demo.

The +task folder in the project has the scripts to automate different activities. The following image shows the summary of activities and dependencies listed inside a MATLAB project. For more information about MATLAB projects, see What Are Projects?

The model focZynqC (or focZynqCFO) automatically computes the ADC (or current) offset values after deployment. To disable this functionality (enabled by default), update the value 0 to the variable paramAdcEnablecalibration in the model initialization script or data dictionary. If you disable this functionality, you can compute the ADC offset manually and update it in the paramAdcCountAtZeroAmpere variable available in the model initialization script.

The MATLAB project includes the resources for both sensor-based and sensorless position estimation techniques. You can configure the project shortcuts to use resources for either one of these techniques:

3. Click the t1_openSimulationTestBenchModel project shortcut or use the following MATLAB command to open either focZynqTestBench (for sensor-based position estimation) or focZynqTestBenchFO (for sensorless position estimation) model.

The Motor_And_Load subsystem consists of a mathematical model of two surface PMSMs (one from Motor Control Blockset and the other from Simscape Electrical), motor load, encoder, and current sensor. The Controller_Algorithm subsystem includes an algorithm for I/O engineering unit conversion, an electrical position calculation algorithm, a rotor velocity calculation algorithm, a mode scheduler, and four control modes (disabled, open loop velocity control, encoder calibration, and closed loop velocity control). The C/D and D/C subsystems convert the data from continuous-time, variable time step solver and floating-point data type, to discrete-time, fixed time step solver and fixed-point data type, and vice-versa during simulation.

For the first two seconds, the controller calibrates the encoder position sensor. The encoder position sensor must be calibrated before the controller can achieve closed loop control. When position calibration begins, the motor accelerates using open loop control in order to identify the index pulse of the encoder.

The hardware part of the design is enclosed in the models focZynqHdl.slx (for sensor-based position estimation) or focZynqHdlFO.slx (for sensorless position estimation). This part uses HDL Workflow Advisor to define and generate an HDL IP core, which includes components such as AXI4 accessible registers, AXI4 interfaces, external ports, and ADC.

Using the HDL Workflow Advisor IP core generation workflow, you insert this IP core into a reference design and generate an FPGA bitstream that runs on the SoC hardware. You can also use the HDL Workflow Advisor to generate a software interface containing AXI driver blocks that connects the embedded software and the FPGA hardware. The example uses external mode to interface with the target model.

You can partition the controller algorithm into sections that separately generate C code (for the designed software) and HDL code (for the designed hardware). See the reports created during the code generation step to determine ways to integrate the generated code and build your application according to your own embedded design.

1. In the focZynqTestBench (for sensor-based position estimation) or focZynqTestBenchFO (for sensorless position estimation) model, open the Controller_Algorithm subsystem. The controller algorithm contains the Algorithm_C and Algorithm_HDL blocks, which reference the following models respectively:

The focZynqC (or focZynqCFO) model contains the portion of the algorithm to be implemented in software (ARM processor). Similarly, the focZynqHdl (or focZynqHdlFO) model contains the portion of the algorithm to be implemented on the FPGA hardware.

3. The Code Generation Report shows how the generated code corresponds to the model. If you are new to the Code Generation report, you can start with the Code Interface Report to view the function interface of the code. The C code is portable and can be integrated with any floating-point embedded processor that uses an ANSI-C compiler. For more information on the Code Generation Report, see Reports for Code Generation (Simulink Coder).

5. The Code Generation Report shows how the HDL code corresponds to the model. If you are new to the Code Generation report, you can start by exploring the Generated Source Files pane of the report and selecting the focZynqHdl.vhd (or focZynqHdlFO.vhd) file that contains the entity specification. The HDL code for the algorithm is portable and can integrate with any FPGA that supports VHDL code.

1. Setup the Xilinx Zynq hardware platform. For information about hardware setup, see Install Support for Xilinx Zynq Platform (Embedded Coder). Install both Embedded Coder Support Package for Xilinx Zynq Platform and HDL Coder Support Package for Xilinx FPGA and SoC Devices.

6. After you program the FPGA bitstream, press the S1 switch located on the motor driver card once to connect the 24V power supply to the MOSFETS. In case of any unexpected behavior from the device, use the S1 switch to disconnect the power.

Use HDL Workflow Advisor to generate the HDL code for the algorithm. Follow these steps to package HDL into an IP core, integrate the IP core into a Xilinx reference design, and then create a bitstream:

3. Select 1.3. Set Target Interface to identify the ports. The Target Platform Interfaces column entries that have the prefix "IP" indicate the connections that are registered with the Trenz motor control reference design.

4. Select 4.3 Build FPGA Bitstream > Run to Selected Task or click the t5_generateBitstreamAndInterfaceBlock project shortcut to generate the HDL code for the algorithm and create the FPGA bitstream from the Xilinx reference design. Alternatively, you can use the following MATLAB command to perform this action:

5. Follow the progress of the bitstream generation on the new DOS command prompt that opens. In addition to generating the bitstream, the customized target generates the focZynqHdlAxiInterfaceLib software interface library. The library contains an AXI_Interface block. The AXI_Interface block, which contains the AXI4-Lite interface components, provides connectivity from the model deployed on the ARM processor to the model deployed on the programmable logic.

6. Run task 4.4 Program Target Device or click the t6_downloadBitstream project shortcut to program the FPGA. Alternatively, you can use the following MATLAB command to perform this action:

You can generate the C code for the controller and automatically integrate this code with a Linux reference framework to build, deploy, and run the model as an executable on the ARM processor. You can then compare the data logged by the model running on the processor with the simulation results.

The focZynqArmDeployment model can generate C code, automatically integrate this code with a Linux ARM reference framework, and deploy the executable to the ARM processor on the Xilinx Zynq platform. The deployable model uses references to the original controller model and contains test stimulus, scope, and AXI_Interface library block that you created in the section Deploy Bitstream to Programmable Logic.

On the Hardware tab, click Monitor & Tune to build, deploy, and run the model as an executable on the ARM processor. The system compiles the generated code against the reference framework to create an executable. During model execution, Simulink monitors the signals and shows them in the scope.

Press the S1 switch located on the Motor Driver card once. This connects the 24V power supply to the MOSFETS, after which the motor should run for 8 seconds. If you see any unexpected behavior in the device, use the S1 switch to disconnect the power.

3. Open the simulation data inspector to view the logged signals and compare them with the signals logged previously from the focZynqTestBench model. You can open simulation data inspector by clicking Data Inspector on the Simulation tab.

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