Hi all,
The reason our makefiles are as complicated as they are is because we're trying to do too much with make. (Marcus, Ben: I'm sure this affects CMake too.)
Make works by specifying a target: that's the thing you want to build. Make then uses rules to build the things needed to build the target, and it does that all the way down.
It shouldn't really be used to kick off executables; that's what we're doing with our test targets. A lot, but not all, of the complication in our makefiles comes from having having the requirement of running the tests as we build them.
So... that's the current state of what's going on. I think there's a way to simplify our makefiles (and hopefully CMake as well), but it might require some changes to how the developers interact from the command line (and I may need some help).
I think if we had a shell script or scripts to execute the tests, we could reduce the complexity of the makefiles. We could even have the shell scripts automatically call the right make target before running the tests. Here's where I'd need help: I'm not good with scripts. And we'd need to make them cross-platform. If we're able to do that, I'd be happy to try to reduce the complexity of our makefiles. And I'd try to get the dependencies working again.
Thoughts? Of course, we can take no action and hopefully implementing CMake will solve it.
Daniel