AppNote 8

[Vaggelis Ntouros]

Hello all,

I was reading the Application Note 8 for interfacing a DVS with an FPGA. I also read http://spinnakermanchester.github.io/docs/fpga_aer/ the implementation described here.

I noticed that even though AER signal (from DVS) is a 5V level signal, no level shifter is used to input the signal in RaggedStone2 FPGA board. According to the user manual the upper threshold is 4.1V and no higher voltage signal should be driven into the FPGA.

Am I missing something? Maybe a level shifter is used and was not mentioned? I am interested in this because I try to implement a similar setup.

Thank you

[Luis Plana Cabrera]

Hi Vaggelis,

You are correct that level shifters are need if the DVS I/O ports operate at 5V.

My understanding is that the DVS that was used (from Instituto de Microelectrónica, Universidad de Sevilla) operates its I/O ports at 3.3V. This was connected directly to pins on the RaggedStone 3.3V I/O bank.

Take care,

-lap

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From: spinnak...@googlegroups.com <spinnak...@googlegroups.com> on behalf of Vaggelis Ntouros <vaggeli...@gmail.com>
Sent: 02 December 2021 09:10
To: SpiNNaker Users Group <spinnak...@googlegroups.com>
Subject: [SpiNNaker Mailing List] AppNote 8

 

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