Using Sphinx documentation for SystemVerilog modules/classes

[Misky H]

Hello,

I am trying to use Sphinx to do auto document systemverilog rtl modules and uvm verification environment.

I found this example on sphinx verilog domain: https://sphinx-verilog-domain.readthedocs.io/en/latest.

Questions I have: 

1) can the  rst files be auto generated similar to python modules/classes?

2) if i am not interested in drawing the hdl and only required the comments to be pulled into the html what else is required in addition to the sphinx_verilog_domain extension.

I am new to using Sphinx and so whatever advice is greatly appreciated.

Thanks