Compiling an application for the zedboard

[Thom Popovici]

Hello

I compiled the normal InnerProduct with FixPt and it seemed to be working, however when trying to make the actual file to get the tar ball that needs to go on the actual FPGA the following error appeared:

mv bigIP.tcl verilog-zedboard/

rm: cannot remove 'gen/PIR/bigIP.tcl': No such file or directory

cp: cannot stat '/home/dtpopovici/tucson/spatial/gen/PIR/bigIP.tcl': No such file or directory

Makefile:31: recipe for target 'hw' failed

make: *** [hw] Error 1

Not quite sure what this means.

Best regards,

Thom

[Matt F]

Hi Thom,

bigIP.tcl should get generated when sbt compiles the chisel -> verilog (sbt "runMain spatialIP.Instantiator --verilog --testArgs zedboard"), which should run right before "mv bigIP.tcl verilog-zedboard."  As the chisel is compiled, it spits out any relevant tcl commands to bigIP.tcl for things like generating multiplier and divider IPs.

Are there any hints in the warnings or errors that appear before this line?  I would guess that chisel compilation failed somehow.  If the chisel did compile (verilog-zedboard/ has a file called SpatialIP.v and it looks like proper verilog), then it must be something with how we are using scala to write this file while chisel compiles.  Let me know if this helps or if things are still breaking.

[Thom Popovici]

Hi

So the bigIP.tcl gets generated and it is in the folder. 

However the second lines are the ones that give problems, rm on gen/PIR/bigIP.tcl and cp: cannot stat '/home/dtpopovici/tucson/spatial/gen/PIR/bigIP.tcl'

When I do make I am within the gen/<application name> so not sure why there is an rm with gen/PIR, and I looked down the tree and there is no folder PIR in gen/.

Hope this makes sense.

[Thom Popovici]

Hi.

I think I found what the problem is... libisl is missing.

Thanks a lot for the fast response.

Best,

Thom

[Thom Popovici]

Hello

I have installed the libisl, however the error persists.

Best,

Thom

[Matt F]

Hi Thom,

One thing I'm not sure about is why things are getting generated in gen/PIR instead of just gen/.  Is there any chance you have the --pir flag on?  I almost never actually compile for PIR personally so I'm not sure if that would cause this.  Is there a verilog-*/SpatialIP.v file generated at the time that the make job crashes?  Maybe if you zip up and send the generated directory for this app, I can poke around and see if there is anything suspicious.