Hi,
Sorry for the delay and the strange error. The quick fix for this problem is to change the app from:
```
val update = if (r == 0) (sw_tuple(0, 0)) else if (c == 0) (sw_tuple(0, 1)) else {
val match_score = mux(seqa_sram_raw(c-1) == seqb_sram_raw(r-1), MATCH_SCORE.to[Int16], MISMATCH_SCORE.to[Int16])
val from_top = score_matrix(r-1, c).score + GAP_SCORE
val from_left = previous_result.score + GAP_SCORE
val from_diag = score_matrix(r-1, c-1).score + match_score
mux(from_left >= from_top && from_left >= from_diag, sw_tuple(from_left, SKIPB), mux(from_top >= from_diag, sw_tuple(from_top,SKIPA), sw_tuple(from_diag, ALIGN)))
}
```
to:
```
val tmp = if (r == 0) (sw_tuple(0, 0)) else (sw_tuple(0, 1))
val update = if (c == 0 || r == 0) (tmp) else {
val match_score = mux(seqa_sram_raw(c-1) == seqb_sram_raw(r-1), MATCH_SCORE.to[Int16], MISMATCH_SCORE.to[Int16])
val from_top = score_matrix(r-1, c).score + GAP_SCORE
val from_left = previous_result.score + GAP_SCORE
val from_diag = score_matrix(r-1, c-1).score + match_score
mux(from_left >= from_top && from_left >= from_diag, sw_tuple(from_left, SKIPB), mux(from_top >= from_diag, sw_tuple(from_top,SKIPA), sw_tuple(from_diag, ALIGN)))
}
```
It looks people have only built this app for fpga and not simulation. The problem is that the `if (a) x else if (b) y else z` pattern turns into a one hot mux, which is generated by producing all 3 results and or-ing them together. In this case, x, y, and z are struct type. In the fpga backend, we just treat the structs as concatenated ints and perform | bitwise. In the scala backend, we treat structs a little differently (as case classes) and | isn't defined. I will fix this in the next Spatial update, but for now you can just change the above to get moving. It just turns the 3-input one hot mux into a cascade of two 2-input muxes, which codegen properly for structs in the scala backend. Thanks for pointing this out!