Does Spatial base on Vivado 2017.1 only?

[Hui Zhang]

I previously had a issue with Vivado 2017.4 when using the aws-sim target because of missing options in Makefile.vivado, then I switched back to 2017.1, But does it support higher version of Vivado?

Thanks

[Matt F]

Hi.  We haven't changed any of the tcl scripts to be compatible with newer versions of Vivado.  I'm not sure what breaks with newer versions, but I would guess it is related to a few lines in the tcl scripts that can be changed.

[Hui Zhang]

Hi, Matt

I'm trying to get Spatial working with the latest aws-fpga. The F1 instance has the latest AMI 1.50 and Vivado 2018.2 installed.

I dug into the Makefile in the gen folder of Spatial and found out that Spatial uses cl_dram_dma example as a template (glue code) for Spatial generated CL. So first, I copied cl_dram_dma from the old aws-fpga branch that Spatial is based on and tried it within the new aws-fpga framework and the new Vivdado 2018.2. It works. So I think the design code you borrowed from that example should still be good with the new aws-fpga and Vivado. Then, I ran Spatial as before, but synthesizing stopped after a few minutes. Here's the error message I found in 19*.vivado.log file:

INFO: [Synth 8-6155] done synthesizing module 'axi_infrastructure_v1_1_0_vector2axi' (28#1) [/home/centos/src/project_data/aws-fpga/hdk/common/shell_v04261818/design/ip/axi_register_slice_light/hdl/axi_infrastructure_v1_1_vl_rfs.v:474]

INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_15_axi_register_slice' (29#1) [/home/centos/src/project_data/aws-fpga/hdk/common/shell_v04261818/design/ip/axi_register_slice_light/hdl/axi_register_slice_v2_1_vl_rfs.v:2300]

INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice' (30#1) [/home/centos/src/project_data/aws-fpga/hdk/common/shell_v04261818/design/ip/axi_register_slice/synth/axi_register_slice.v:58]

ERROR: [Synth 8-5809] Error generated from encrypted envelope. [/home/centos/src/project_data/aws-fpga/hdk/cl/examples/Hui_HelloSpatial_hw/build/src_post_encryption/cl_dram_dma.sv:1004]

ERROR: [Synth 8-5809] Error generated from encrypted envelope. [/home/centos/src/project_data/aws-fpga/hdk/cl/examples/Hui_HelloSpatial_hw/build/src_post_encryption/cl_dma_pcis_slv.sv:16]

ERROR: [Synth 8-5809] Error generated from encrypted envelope. [/home/centos/src/project_data/aws-fpga/hdk/cl/examples/Hui_HelloSpatial_hw/build/src_post_encryption/cl_dram_dma.sv:18]

I backtracked the log file and found the most recent WARNING to the error, not sure if it helps:

Running synth_design for cl_dram_dma /home/centos/src/project_data/aws-fpga/hdk/cl/examples/Hui_HelloSpatial_hw/build/scripts [Wed Feb 06 18:42:43 2019]

Command: synth_design -top cl_dram_dma -verilog_define XSDB_SLV_DIS -part xcvu9p-flgb2104-2-i -mode out_of_context -keep_equivalent_registers -flatten_hierarchy rebuilt -max_uram_cascade_height 1 -directive default

Starting synth_design

WARNING: [Vivado_Tcl 4-391] The following IPs are missing output products for Implementation target. These output products could be required for synthesis, please generate the output products using the generate_target or synth_ip command before running synth_design.

/home/centos/src/project_data/aws-fpga/hdk/common/shell_v04261818/design/ip/axi_register_slice_light/axi_register_slice_light.xci

/home/centos/src/project_data/aws-fpga/hdk/common/shell_v04261818/design/ip/axi_register_slice/axi_register_slice.xci

/home/centos/src/project_data/aws-fpga/hdk/common/shell_v04261818/design/ip/dest_register_slice/dest_register_slice.xci

/home/centos/src/project_data/aws-fpga/hdk/common/shell_v04261818/design/ip/src_register_slice/src_register_slice.xci

Do you have any clues of what the problem could be? Thanks