La-6842p Schematic

[Mariam Obregon]

ToshibaSatellite C660 Compal LA-6842P PWWAA LC Marselle Rev:0.2 schematic diagram.We are believing in reviving the technology and making minimum electronics waste, as our field is computers and laptops we are here trying to provide as much stuff as possible for free to make our contribution. At this platform you can download schematics diagram and other relative material to make it possible to repair.

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Hi all dear members

I have designed my first PCB in Kicad. It is such an isolated interface board with capability of CAN & RS485 & RS232 communications and is free for using every one who will be interested in it

I really appreciate any kind of recommendations and advice for better design and really eager to get your valuable comments .

It is detrimental to stack capacitors of low ESR next to each other[1]. They create resonances between each other that can cause high impedance for specific frequencies. This allows noise at this frequency into your circuit where it would not have existed with a single capacitor value.

Note that there are long loops and fingers in the ground plane with no vias to connect it to the top ground plane. This will create resonant antennas as current flows preferentially through one plane, causing current to flow in the opposite direction in the other.

I see quite a lot of things I like, bunch of things that can be improved (No wonder for a first design) and a whole lot of things I do not understand. Can you tell us a bit more about the intended use of this design?

The overall design looks like a development board, but for a development board I would expect connectors on all unused I/O pins. The pins on the STM32F407VGTx are pretty small, and it is a nuisance to solder wires to them later. You also have plenty of room on the PCB to add some 0.1" breakout headers.

I like the grouping by functionality on the schematic. Did you follow the guidelines from the EEvblog video there? I like the fat blue text for different function blocks, but the blue dotted lines are a bit overkill, I tried that once also, and the tend to get moved and redrawn a lot, which is mostly a waste of time.

You have a clear isolation barrier on the PCB, which is very good. But I would like that same barrier on the schematic. If you want to blue dotted lines on the schematic, then use it for the isolation barrier. For example, I think these voltages are on different parts of the isolation barrier:

image717170 2.66 KB

(I removed the bold attribute from one of the labels, makes it easier to read).

You have a separate block with connectors, and it is not clear what they do. It is much more logical to put the connectors with the function blocks where they belong. Put the RS485 connector in the RS485 block.

I like the TVS diodes.

I like the ferrite bead, but I want to see more of them. Especially where te power comes into the board. The uC is easily upset by (very short) spikes, and these short spikes go right through the voltage regulator.

Reset switch:

100nF directly shorted with a switch that can probably only handle 50mA or so is not a robust design. For a reset switch that only gets used occasionally this is less of a problem than for example a rotary encoder, but it still is bad practice. Assume such a small ceramic capacitor can deliver a 10A peak current.

You have made the Zones for the GND planes the same size as the board outline.

This is not so good. It makes the zones harder to select. KiCad should always respect a clearance between the board outline and the edge of the zones. It is better to make the zone 1 or 2mm smaller than the board. Alternatively, I often make the zones a lot bigger then the board outline, and with some slanted or jagged edges. If anything then goes wrong during Gerber generation you see it immediately. With making the zones and board outline the same, you risk having the zones to the edge of the board, which can lead to manufacturing problems (Shorts around board edges).

You also have the connector J4 directly connected to the GND plane (although not connected very solidly). Preferably both GND and VDD5v_68K go through a common mode filter (or at least ferrite beads & ceramic capacitor) and then only connect to the voltage regulator section before a connection to the GND plane is made. Keep external noise away from the GND plane.

Piotr is right that an 0805 resistor can not handle 20A DC, but the current spikes are short. PSM712 is also only rated for short pulses. For protecton devices like these resistors it is also common to use bigger packages such as 1206 or 2510 which can absorb more energy before they get overheated.

I design 2 layer PCB in such way that I have all connections except GND on top layer, and whole bottom is GND.

Imagine digital signal connection from source to load goes 3cm up and then 4cm right. The DC back current would go back directly by third side (5cm) of triangle, but the higher is the digital signal component the more it likes to go back directly under the original signal track. It is very good as the area surrounded by the signal is smaller = much less emission and much less sensitivity. Understand the sorrounded area as receiving/emission antenna. If current can go back under the track the area (looking from top) is 0 (looking from side the PCB thickness becomes important).

That works if the back current has a copper to go back as he wonts, but at your PCB it has not.

Go with VCC that way and it is possible that you will be able to make all connections without any via (except GND). That is because going with VCC to all VCC/GND microcontrroller pairs is what disturbes all other signals. If some lines crosses I use other microcontroller pins if possible (I use ATXmega where for example SPI pins can be swapped by software).

You are right. The better example could be lines to RS485, but there return paths were better

I just wonted to show how to look at that. I have heared that it happened that 1kHz signal made device to have to much emission at some handred MHz range as the dU/dt is more important than frequency and current ICs have high dU/dt at their outputs.

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