Modern Processor Design: Fundamentals Of Superscalar Processors John Paul Shen
Giovanna Qiu
The text presents fundamental concepts and foundational techniques such as processor design, pipelined processors, memory and I/O systems, and especially superscalar organization and implementations. Two case studies and an extensive survey of actual commercial superscalar processors reveal real-world developments in processor design and performance. A thorough overview of advanced instruction flow techniques, including developments in advanced branch predictors, is incorporated. Each chapter concludes with homework problems that will institute the groundwork for emerging techniques in the field and an introduction to multiprocessor systems. Not-for-sale instructor resource material available to college and university faculty only; contact publisher directly.
With the emergence of superscalar processors, phenomenal performance increases are being achieved via the exploitation of instruction-level parallelism (ILP). Software tools for aiding the design and validation of complex superscalar processors are being developed. These tools, such as VMW (Visualization-Based Microarchitecture Workbench), facilitate the rigorous specification and validation of microarchitectures.
Modern Processor Design: Fundamentals of Superscalar Processors John Paul Shen
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Microarchitecture and code transformation techniques for effective exploitation of ILP are being studied. Synergistic combinations of static (compile-time software) and dynamic (run-time hardware) mechanisms are being explored. Going beyond a single instruction stream is necessary to achieve effective use of wide superscalar machines, as well as tightly coupled small-scale multiprocessors.
Conceptual and precise, Modern Processor Design brings together numerous microarchitectural techniques in a clear, understandable framework that is easily accessible to both graduate and undergraduate students. Complex practices are distilled into foundational principles to reveal the authors insights and hands-on experience in the effective design of contemporary high-performance micro-processors for mobile, desktop, and server markets. Key theoretical and foundational principles are presented in a systematic way to ensure comprehension of important implementation issues.
The text presents fundamental concepts and foundational techniques such as processor design, pipelined processors, memory and I/O systems, and especially superscalar organization and implementations. Two case studies and an extensive survey of actual commercial superscalar processors reveal real-world developments in processor design and performance. A thorough overview of advanced instruction flow techniques, including developments in advanced branch predictors, is incorporated. Each chapter concludes with homework problems that will institute the groundwork for emerging techniques in the field and an introduction to multiprocessor systems.
John Paul Shen was a Nokia Fellow and the founding director of Nokia Research Center - North America Lab. NRC-NAL had research teams pursuing a wide range of research projects in mobile Internet and mobile computing. In six years (2007-2012), NRC-NAL filed over 100 patents, published over 200 papers, hosted about 100 Ph.D. interns, and collaborated with a dozen universities. Prior to joining Nokia in late 2006, John was the director of the Microarchitecture Research Lab at Intel. MRL had research teams in Santa Clara, Portland, and Austin, pursuing research on aggressive ILP and TLP microarchitectures for IA32 and IA64 processors. Prior to joining Intel in 2000, John was a tenured Full Professor in the Department of Electrical and Computer Engineering at Carnegie Mellon University, where he supervised a total of 17 Ph.D. students and dozens of M.S. students, received multiple teaching awards, and published two books and more than 100 research papers. One of his books, Modern Processor Design: Fundamentals of Superscalar Processors, was used in the EE382A Advanced Processor Architecture course at Stanford, where he co-taught the EE382A course. After spending 15 years in industry, all in Silicon Valley, he returned to Carnegie Mellon in the fall of 2015 as a tenured full professor in the ECE Department and is based at the Carnegie Mellon Silicon Valley campus.
Shen's broad technical expertise encompasses computer architecture and processor design, mobile and ubiquitous computing, mobile sensing and user behavior modeling, web-based software systems and services, wireless based cloud computing infrastructure, and power and energy efficient supercomputing. His current research interests include modern processor design and evaluation, architecture and compilation for instruction-level parallelism, and dependable and fault-tolerable computing.
He has published over 100 research papers in diverse areas, including fault-tolerant computing, built-in self-test, process defect and fault analysis, concurrenterror detection, application-specific processors, performance evaluation, compila-tion for instruction-level parallelism, value locality and prediction, analytical mod-eling of superscalar processors, systematic microarchitecture test generation, per-formance simulator validation, precomputation-based prefetching, database workloadanalysis, and user-level helper threads.
This book emerged from the course Superscalar Processor Design, which has beentaught at Carnegie Mellon University since 1995. Superscalar Processor Design is a mezzanine course targeting seniors and first-year graduate students. Quite a few ofthe more aggressive juniors have taken the course in the spring semester of their jun-ior year. The prerequisite to this course is the Introduction to Computer Architecturecourse. The objectives for the Superscalar Processor Design course include: (1) toteach modem processor design skills at the microarchitecture level of abstraction;(2) to cover current microarchitecture techniques for achieving high performance viathe exploitation of instruction-level parallelism (ILP); and (3) to impart insights andhands-on experience for the effective design of contemporary high-performancemicroprocessors for mobile, desktop, and server markets. In addition to covering thecontents of this book, the course contains a project component that involves themicroarchitectural design of a future-generation superscalar microprocessor.
During the decade of the 1990s many microarchitectural techniques for increas-ing clock frequency and harvesting more ILP to achieve better processor perfor-mance have been proposed and implemented in real machines. This book is anattempt to codify this large body of knowledge in a systematic way. These techniquesinclude deep pipelining, aggressive branch prediction, dynamic register renaming,multiple instruction dispatching and issuing, out-of-order execution, and speculativeload/store processing. Hundreds of research papers have been published since theearly 1990s, and many of the research ideas have become reality in commercialsuperscalar microprocessors. In this book, the numerous techniques are organizedand presented within a clear framework that facilitates ease of comprehension. Thefoundational principles that underlie the plethora of techniques are highlighted.
Chapter 4: Superscalar OrganizationThis chapter introduces the main concepts and the overall organization of superscalarprocessors. It provides a "big picture" view for the reader that leads smoothly into thedetailed discussions in the next chapters on specific superscalar techniques for achiev-ing performance. This chapter highlights only the key features of superscalar processororganizations. Chapter 7 provides a detailed survey of features found in real machines.
Chapter 5: Superscalar TechniquesThis chapter is the heart of this book and presents all the major microarchitecture tech-niques for designing contemporary superscalar processors for achieving high perfor-mance. It classifies and presents specific techniques for enhancing instruction flow,register data flow, and memory data flow. This chapter attempts to organize a plethoraof techniques into a systematic framework that facilitates ease of comprehension.
Chapter 7: Intel's P6 MicroarchitectureThis is a case study chapter on probably the most commercially successful contempo-rary superscalar microarchitecture. It is written by the Intel P6 design team led by BobColwell and presents in depth the P6 microarchitecture that facilitated the implemen-tation of the Pentium Pro, Pentium n, and Pentium in microprocessors. This chapteroffers the readers an opportunity to peek into the mindset of a top-notch design team.
Chapter 8: Survey of Superscalar ProcessorsThis chapter, compiled by Prof. Mark Smotherman of Clemson University, pro-vides a historical chronicle on the development of superscalar machines and a survey of existing superscalar microprocessors. The chapter was first completed in1998 and has been continuously revised and updated since then. It contains fasci-nating information that can't be found elsewhere.
In summary, Chapters 1 through 5 cover fundamental concepts and foundation-al techniques. Chapters 6 through 8 present case studies and an extensive survey ofactual commercial superscalar processors. Chapter 9 provides a thorough overviewof advanced instruction flow techniques, including recent developments in ad-vanced branch predictors. Chapters 10 and 11 should be viewed as advanced topicschapters that highlight some emerging techniques and provide an introduction tomultiprocessor systems.
This book focuses on contemporary superscalar microprocessor design at themicroarchitecture level. It presents existing and proposed microarchitecture tech-niques in a systematic way and imparts foundational principles and insights, withthe hope of training new microarchitects who can contribute to the effective designof future-generation microprocessors.
With scalar pipelined processors, there is still the limitation of fetching andinitiating at most one instruction into the pipeline every machine cycle. With thishmitation, the best possible CPI that can be achieved is one; or inversely, the bestpossible throughput of a scalar processor is one instruction per cycle (IPC). A more aggressive form of instruction-level parallel processing is possible thatinvolves fetching and initiating multiple instructions into a wider pipelined proces-sor every machine cycle. While the decade of the 1980s adopted CPI = 1 as itsdesign objective for single-chip microprocessors, the goal for the decade of the1990s was to reduce CPI to below one, or to achieve a throughput of IPC greaterthan one. Processors capable of IPC greater than oneare termed superscalar pro;cessors. This section presents the overview of mstruction-level parallel processingand provides the bridge between scalar pipelined processors and their naturaldescendants, the superscalar processors.
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