MoM of today's OCP SONiC call 06/18/2019.Topics discussed
- Error Handling - BRCM (Santhosh)Review (Q&A)We had a great discussion, there are lot of inputs from community and here is some. Feel free to add missing comments here.
- How does framework supports multiple CRUD failures?
- Do you provide a knob to switch off Error handling feature? Is knob necessary?
- Does the applications get out of order notifications from feedback loop? How to handle in the case of it? Ex: User does create/delete/create and do you expect the error feedback come in order?
- What is the design decision behind a new Error DB? Why can't we merge error attributes into APP DB?
- What is the mechanism to synchronize route CRUD between APP DB vs new Error DB?
- Is new Error DB is a mirror of APP DB?
- The current design mentioned an approach to stop propagate the failed/error routes to the neighbors? This may not right as per RFC, the routes should propagate though the it failed due to some policy. (Nikos)
Overall feedback - The feedback loop is necessary to address SAI fatal errors. However the community requested the design should dis associate/de couple the feedback loop as much as possible so that applications have freedom to react/handle it own way.
one option suggested - Framework should more generic and should accommodate opaque error context for the applications.
Xin will extend an offline discussion on this topic, stay tuned.Announcements
- SONiC Release 201908 tracking page - Xin can you post the link
- Action Item for community - Signup for PR reviewsMoM of today's OCP SONiC call 06/04/2019.Topics discussed
- STP/PVST - Sandeep (BRCM)Q & A
- Can this STP feature compile time disabled? BRCM will explore this (compile time/run time options to disable/enable STP/PVST feature)
- Warm reboot not supported for PVST? Community requested more details need to be added to design
- Multiple questions what is the design decision on why STP states are not programming to Kernel? Few questions: 1) With the current STP design - the STP states are not populating in kernel, ASIC and Kernel will be out of sync, what is the downside ? 2) Let's say Port/Vlan is not blocking in the kernel, but is blocked in ASIC, then what is the behavior with arp/ping/ospf in this scenarios ? BRCM should document the scenarios.
- Community requested to document the ASIC and Kernel out of sync scenarios - AI BRCM
- There should be no drop if HW says forwarding? yes
- Is there mechanism to program the states in to Kernel ? BRCM to explore on it
- If the trap is configured on port which is blocked does the packet comes to CPU? yes, based on the trap configurations.
- When port is blocked in HW, what are the packets should send? - HW shouldn't block L2 packets/LACP exchanges but drop L3 packets.
- Can COPP program to trap to cpu ? Yes
- HLD on NAT - Kiran Kella (BRCM)Q & A
- Does it support payload/embedded headers (ALGs- application level gateways) support ? Not right now.
- Continue discussion next sub group meeting.Announcements
- Next sub group meetings HLD on NAT, SFLow