DASH Workgroup Community Update 7/23/2025

[Kristina Moore]

Hello DASH Community –thank you for your time last Wednesday.  

We continue to have a potential contribution back up for grabs.  It would be great to have a volunteer to suggest a PR in the dash-sonic-hld (in the SONiC repo here) for commands to show ENI counters and DPU global metrics – please submit a PR if you are interested!

 

The PR/Issue development turnaround continues; we Merged 21 PRs across multiple SONiC repos this week related to SmartSwitch HW, testing, and HA (please see full list below). 

@Bud Grise from XSight Labs presented their new DPU, the E1, highlighting its specifications and performance in the DASH project. The E1 is a 5-nanometer chip with 64 cores, 40 lanes of PCIE Gen. 5, and two 400 Gigabit Ethernet ports. It has passed the HERO 800 test, processing 120 million background flows and 12 million connections per second of foreground TCP flows for 100 seconds with 0 drops.  Please reach out to Bud if you are interested in further discussing the hardware. 

 

For Floating ENI mode, we have committed an additional field in the ENI table object to support the Floating ENI mode. Tests are also being written to verify the functionality of multiple ENIs in different modes on the same DPU.

 

OCP 2025 is coming up in October 2025; we encourage our group to partner on issues or talks to present if you are interested.  You can join the mailing list at sonic-o...@lists.sonicfoundation.dev in order to receive further information.  Please find below the timelines, and details that I’ve seen. 

 

Timelines

Talks CFP Opens: Now (opened May 29, 2025) (https://sessionize.com/sonic-events-ocp-25/)

Talks CFP Closes: Jul 27, 2025

Interest & Workgroup Meeting CFP Opens: Jul 21, 2025 (via email to bri...@google.com, ry...@nexthop.ai, sup...@sonicfoundation.dev )

Interest & Workgroup Meeting CFP Closes: Aug 4, 2025

Schedule Announced: Week of August 10, 2025

 

•             Thursday, Oct 16 - SONiC Workshop @ OCP

•             Friday, Oct 17 - SONiC Workshop @ Google 

 

Meeting Details for Working Groups

The morning program will be dedicated to submitted talks. For the afternoon, there is planning for working groups to meet in person for 30-90 minute sessions (with a Google Meet invitation to these events to accommodate virtual attendees).

 

Suggested Topics for Working Group Sessions

Here are a few ideas:

•             Design Reviews

•             Roadmap Planning

•             Brainstorming

•             Team Building

Call for Participation

If your working group is interested in meeting during the extended workshop, please reply with the following by Monday, August 4:

•             Session leader name:

•             Session leader company:

•             Session leader email:

•             (optional) Session co-leader name:

•             (optional) Session co-leader company:

•             (optional) Session co-leader email:

•             A 2-3 sentence pitch to advertise your session

•             A short agenda for your session (3-4 bullet points is sufficient)

•             Your expected in-person headcount (< 10, 10-20, 20-30, > 30)

•             Your preferred session length (30, 60, 90 min)

•            

Examples of workgroups are: AI, Chassis, Common Infrastructure, DASH, Documentation, Layer-1, OCS, Optical Transport Network (OTN), Pens, Platform OS, Routing, Routing: PhoenixWing Testing, Scale Up, Security, Smartswitch, Test, Unified Management Framework (UMF), Virtual Data Plane (VDP).    

You are also welcome to propose a session that does not map to a current SONiC working group, which the TSC will consider if there is available space.  Please follow the same template for submissions.

Reminder: This is a vendor-neutral community event — no product or vendor sales pitches. Avoid sales or marketing pitches and discussing unlicensed or potentially closed-source technologies when preparing your proposal; these talks will not be accepted due to the fact that they take away from the integrity of the events, and are rarely well-received by conference attendees.

By submitting, you agree to The Linux Foundation's Code of Conduct


Follow-up tasks:

• ENI VXLAN Source Port Range Documentation and Testing: Document the VXLAN source port range constraint and create a corresponding test for it. (Michal/Prince)
• Object Versioning Validation: Create a work item to validate that versioning is present wherever needed for all objects to avoid unnecessary recompilation when checking state. (Kristina)
• Floating ENI Modeling and Testing: Ensure that the Floating ENI property is correctly modeled on the ENI (not switch) level, update documentation as needed, and verify that tests cover programming multiple ENIs in different modes on the same DPU. (Michael, Senthilnathan)

• ZMQ Reconnect Test Case: Verify the test case for ZMQ reconnect functionality. (Prabhat)

 

        

In Summary (full list below), since the last Community call we have:

21 PRs Completed (+8)

9 in To Do (+/- 0)

6 in Draft (+ 2)

31 in Progress (+2)

6 Awaiting Review (+2)

Just a reminder that we would encourage/invite Community members to present to the Community (test runs or progress, new scenarios, etc…), just ‘r’ to let me know, or generate a PR in the repo.

The DASH YouTube channel link is here to subscribe / access WG content (and click the bell to receive notifications). 

Thank you for your time/contributions – see you on 7/30/2025

 

SONiC-DASH-Workgroup Community Meeting #154

Attendees (15):

DASH Group to join: https://groups.google.com/g/sonic-dash

Linux Foundation list: https://lists.sonicfoundation.dev/g/SONiC-Dash

 

 

 

 Full DASH Community Notes 😊  

• XSight Labs Presentation: Bud Grise from XSight Labs presented their new DPU, the E1, highlighting its specifications and performance in the DASH project. The E1 is a 5-nanometer chip with 64 cores, 40 lanes of PCIE Gen. 5, and two 400 Gigabit Ethernet ports. It has passed the HERO 800 test, processing 120 million background flows and 12 million connections per second of foreground TCP flows for 100 seconds with 0 drops.
• XSight Labs Background: Bud Grise introduced XSight Labs as a networking ASIC vendor with engineers from Easy Chip, Cisco, and Broadcom. They have extensive data plane experience and two main products: the X2 switch and the E1 DPU.
• E1 Specifications: The E1 is a 5-nanometer chip with 64 server-class cores, 40 lanes of PCIE Gen. 5, and two 400 Gigabit Ethernet ports. It supports up to half a terabyte of RAM and includes inline and look-aside crypto for storage acceleration.
• HERO 800 Test: The E1 passed the HERO 800 test, processing 120 million background flows and 12 million connections per second of foreground TCP flows for 100 seconds with 0 drops, exceeding the requirement by 19%.
• Development Timeline: XSight Labs received their first E1 chips in March, shipped evaluation boards 10 weeks later, and have been sampling to multiple customers. They re-engaged with the DASH project after receiving silicon.
• E1 Performance and Development:
• Performance Capabilities: The E1 can handle 800 gigabits per second as a bump in the wire and supports high performance in AI NIC use cases. It has 4 DDR5 memory channels and can process hundreds of millions of packets per second.
• Architecture Details: The E1's architecture includes a hardware RX pipeline, N2 cores, and a TX pipeline. It scales out data paths, DMA engines, and compute to support high performance, with a programmable hardware pipeline for additional optimization.
• Development Environment: The E1's development environment is user-friendly, resembling a server with DPDK drivers. Developers can use the same code base without needing to rewrite the data plane or control plane code, minimizing new logic bugs and race conditions
• Development Flexibility: The development approach for the E1 allows for flexibility in performance optimization. Developers can port existing applications, check performance, and use hardware lookup tables for further optimization if needed.
• Development Tools: The E1 supports standard development and debugging tools, allowing developers to write in any language and use familiar tools. The data plane is a DPDK application written in C and C++.
• Porting Process: The data plane was originally developed on X86 hardware, ported to an Ampere ARM server in a day, and then ported to the E1 in another day.
   
• HERO 800 Test Results: Shared the results of the HERO 800 test, where the E1 processed 120 million background flows and 12 million connections per second of foreground TCP flows for 100 seconds with 0 drops. The E1 exceeded the requirement by 19%, using only 55 of its 64 cores for the data plane.
• Test Configuration: The HERO 800 test involved 128 ENIs with a large configuration of routes, mappings, and ACLs. The configuration was side-loaded from a local JSON file with 300 million lines, optimized to load in 6 minutes.
• Test Results: The E1 processed 120 million background flows and 12 million connections per second of foreground TCP flows for 100 seconds with 0 drops, exceeding the requirement by 19% and using only 55 of its 64 cores for the data plane.
• Performance Optimization: The E1's programmable hardware RX pipeline was not used for the HERO 800 test. If used, it could increase throughput by another 25%. This flexibility allows for performance optimization based on specific needs.
• Community Project Updates: Ongoing work and contributions. She mentioned the addition of PLNSG tests, Smart switch UHD config support, and the implementation of PL Redirect map.
• Floating ENI Mode: Michal and Senthilnathan discussed the Floating ENI mode, with Senthil confirming that Lawrence committed an additional field in the ENI table object to support the Floating ENI mode. Tests are being written to verify the functionality of multiple ENIs in different modes on the same DPU.
• Floating ENI Support: This update allows for the configuration of ENIs in Floating mode.
• Testing Multiple ENIs: Tests are being written to verify the functionality of multiple ENIs in different modes on the same DPU. This ensures that the DPU can handle ENIs in both Floating and non-Floating modes simultaneously.
• Follow-up on Action Items:
• Floating ENI Design: Michal and Kristina discussed the need to follow up on the Floating ENI design. Kristina agreed to create a work item to ensure it is addressed.
• Versioning Validation: Agreed to create a work item to validate the versioning of objects. This validation will ensure that versioning is correctly implemented where needed.
• OCP and Future Sessions: Mentioned the upcoming OCP event and the possibility of having sessions there. She encouraged participants to bring up any issues or topics they wanted to discuss.

 

Sticky for Links/Reference:
DASH Groups to join to receive Invites, Meeting Notes, and Comms	DASH: https://groups.google.com/g/sonic-dash     DASH-Test-Workgroup Group: https://groups.google.com/g/sonic-dash-test-workgroup   Linux Foundation list: https://lists.sonicfoundation.dev/g/SONiC-Dash	If anyone knows other people who would like info re: our community, please have them joins these groups for receive Comms, etc…
Links to Recording	Teams/Sharepoint: SONiC-DASH Workgroup Community Meeting-20250723_090245-Meeting Recording.mp4   DASH Community YouTube: https://youtu.be/IiXxqBu9HUo   HA moved to SmartSwitch LF group on Thursdays YouTube Behavioral Model: none this week	7/23/2025 DASH Community Call; please request access via the link if you are not able to view/listen
Azure DASH GitHub Repo:	https://github.com/sonic-net/DASH
Test/Docs folder:	https://github.com/sonic-net/DASH/blob/main/test/docs/dash-test-workflow-saithrift.md	Ideal test workflow is here, converted to .md
SAI Thrift	SAI Thrift PR	Client server needed for testing
P4	https://opennetworking.org/p4/ and https://p4.org/working-groups/	Open source, domain-specific programming language for network devices, specifying packet processing for data plane devices (switches, routers, NICs, filters, etc.)
PINS	https://opennetworking.org/pins/
PNA consortium spec	https://p4.org/p4-spec/docs/PNA-v0.5.0.html	An architecture describing the structure and common capabilities of network interface controller (NIC) devices which process packets transiting one or more interfaces and a host system. Describes the structure and capabilities of the pipeline, and a user program, which specifies the functionality of the programmable blocks within that pipeline. For more information, see the P4 Language Consortium specifications
IPDK	Infrastructure Programmer Development Kit (ipdk.io) and https://github.com/ipdk-io/ipdk-io.github.io	IPDK is an open source, vendor agnostic framework of drivers and APIs for infrastructure offload and management which runs on a CPU, IPU, DPU or switch. IPDK runs in Linux and uses a set of well-established tools such as DPDK and P4 to enable network virtualization.
bmv2	https://github.com/p4lang/behavioral-model	The second version of the reference P4 software switch, nicknamed bmv2 (for behavioral model version 2). The software switch is written in C++11. It takes as input a JSON file generated from your P4 program by a P4 compiler and interprets it to implement the packet-processing behavior specified by that P4 program
DPDK	https://www.dpdk.org/	DPDK is the Data Plane Development Kit which consists of libraries to accelerate packet processing workloads running on a wide variety of CPU architectures.
Linux Foundation SmartSwitch	https://lists.sonicfoundation.dev/g/sonic-smartswitch/calendar

  

Thank you again for your participation…

Kristina Moore MBA, M.S., CISSP - Azure Core Principal PM / DASH & SmartSwitch
Office: 425-722-7720     Mobile: 425-876-2040     Email: kri...@microsoft.com
DASH Group to join: https://groups.google.com/g/sonic-dash    
Linux Foundation:  https://lists.sonicfoundation.dev/g/SONiC-Dash