Non-inclusive Cache Implementation

[Hyeonggyu Kim]

Hello, all.

I'm now struggling to implement non-inclusive cache using Sniper.

As I understand so far, Sniper has strictly 'inclusive cache' model.

In other words, upper level cache can take the wanted cache line only through lower level cache.

I tried to access DRAM on L1-D Cache miss, but, I encountered a message like It's impossible work because lower level cache doesn't have the copied cache block. (It's not exact message.)

Is there anybody who has implemented non-inclusive cache or similar structure?

Although this is irrelative... is there single-core model that doesn't need the coherency protocol or directory scheme in Sniper?

Regards,

Hyeonggyu

[Wim Heirman]

Hyeonggyu,

If you only have a single last-level cache, you can set perf_model/dram/direct_access=true which means the LLC will access DRAM directly and bypass the directory scheme. There will still be snooping coherency between multiple cores sharing that LLC though.

As for non-inclusive caches, we've never implemented this. I'm sure it's possible, but the assumption of inclusion is made in many places (e.g. both line fill and writeback) so you'll have to find and update all those cases.

Regards,

Wim

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[Hyeonggyu Kim]

Wim,

Thank you for your helpful reply.

Sincerely,

Hyeonggyu