Local vs Remote NUCA access

[Abbas Banaiyan]

Hi,

I need to distinguish between local vs remote NUCA cache accesses in a mesh CMP. 

I found that in dram_directory_cntlr.cc where is the only place that HitWhere::NUCA_CACHE is set, I can hack the code.

I need to do the following check there  if (m_core_id == CacheCntlr::getHome(address)) to distinguish between local vs remote tile id.

However, I don't know how to access the CacheCntlr::getHome(address)) function there.

Thanks,

Abbas

 

[Wim Heirman]

Abbas,

The getHome function is provided by the AddressHomeLookup class. There are two sets of them, one for looking up tag directory and NUCA slice locations, and another one for looking up DRAM controller locations. Both are constructed by the MemoryManager class, and pointers are passed out to various classes that use this functionality.

Currently the DramDirectoryCntlr constructor only gets a pointer to the second AddressHomeLookup (see memory_manager.cc, line 259). So you'll also want to pass it the m_tag_directory_home_lookup pointer as well. You can then call m_tag_directory_home_lookup->getHome(address) from inside DramDirectoryCntlr.

Note that in DramDirectoryCntlr, m_core_id means the tile where this tag directory (and NUCA cache) slice is located. So m_core_id == getHome(address) will always match since this code is executing at the home tile. Instead you'll want to compare with the core_id that made the request, which is in the receiver variable.

Regards,

Wim

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[Abbas Banaiyan]

Thanks for your detailed response. It was very helpful.

Best,

Abbas

[Zilmarij Iqbal]

Hi Wim,

I am working with 4x4 NUCA cache based architecture and am trying to achieve the following. The data/instructions associated to a particular core/application should be stored in the home NUCA slice rather than be scattered around in other slices (each core runs a single application only). I was trying to achieve the same effect through the following line in AddressHomeLookup::getHome() as follows:

   SInt32 module_num = (address >> m_ahl_param) % num_cores;

This modification makes all the requests go to only one cache_ctlr, which is that of the first NUCA slice.

What I observed that the right operand of the % determines the number of LLC-controllers or NUCA slices to use, and plays no role in segregating the data for the different applications.

Therefore, we need to first make sure that data to slice mapping granularity must be that of a page [1]. The way to achieve that is by setting some immediate address bits after the m_ahl_param  bits to the same value for all the data corresponding to a particular core/app, and then doing the % with the core_id to map it to its home slice.

However, a better way of getting around the problem is to set the required bits immediately after the m_ahl_param to represent the home-core of the address. The information can then be extracted in the same function as above and we can get the required mapping in a cleaner way than the earlier. This also would require modification to the address.

I want to first confirm if my understanding is correct.

If yes, then where and how can I set the required bits in the address?

Thanks

Zilmarij Iqbal

S. Cho and L. Jin, "Managing Distributed, Shared L2 Caches through OS-Level Page Allocation," 2006 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'06), 2006, pp. 455-468, doi: 10.1109/MICRO.2006.31.