Access L2 Cache without Having to Access L1 Cache

[Abdelrahman S. Hussein]

Hello,

I am working on implementing a component in the Memory Manager that needs to access the cache hierarchy starting from L2 NOT L1. So, the access sequence is L2 -> L3 -> DRAM whereas the core still accesses the cache hierarchy from L1 -> L2 -> L3 -> DRAM as normal.

Unfortunately, when I try to access the L2 directyl from this component, I get the following error:

 [2283577]  [ 0]  [cache_cntlr.cc      : 516]  *ERROR* Tried to read in next-level cache, but data is already gone 

This is my code:

hit_where = m_cache_cntlrs[MemComponent::L2_CACHE]->processShmemReqFromPrevCache(nullptr, Core::mem_op_t::READ, curr_addr_aligned,  modeled == Core::MEM_MODELED_NONE || modeled == Core::MEM_MODELED_COUNT ? false : true, modeled == Core::MEM_MODELED_NONE ? false : true, Prefetch::NONE, getShmemPerfModel()->getElapsedTime(ShmemPerfModel::_USER_THREAD), true);

if I try to use processMemOpFromCore(...) instead to access L2, I also get an asseration failure that I cannot access L2 directly.

So, what should I do here?

Thanks