miss rate in LLC

[rollin...@gmail.com]

Hello,

I configure the sniper as an 8-core SMP, and the L3/LLC is shared by all 8 cores. Each core has private L1 & L2 caches.

I got following results after running parsec.canneal, with simmedium as input size.

 Cache L3                           |            |            |            |            |            |            |            |           

    num cache accesses               |        679 |    2454687 |    2456584 |    2458137 |    2453115 |    2453632 |    2461036 |    2459610

    num cache misses                 |        447 |    1129738 |    1131157 |    1131354 |    1129733 |    1130678 |    1131334 |    1131120

    miss rate                        |     65.83% |     46.02% |     46.05% |     46.02% |     46.05% |     46.08% |     45.97% |     45.99%

    mpki                             |      22.20 |       9.47 |       9.47 |       9.47 |       9.47 |       9.47 |       9.45 |       9.46

DRAM summary                         |            |            |            |            |            |            |            |           

  num dram accesses                  |   12520741 |          0 |          0 |          0 |          0 |          0 |          0 |          0

  average dram access latency (ns)   |      74.90 |        inf |        inf |        inf |        inf |        inf |        inf |        inf

  average dram queueing delay        |      21.48 |       0.00 |       0.00 |       0.00 |       0.00 |       0.00 |       0.00 |       0.00

  average dram bandwidth utilization |     64.00% |      0.00% |      0.00% |      0.00% |      0.00% |      0.00% |      0.00% |      0.00%

I read the FAQ(http://snipersim.org/w/Frequently_Asked_Questions) about the cache miss rate. So in my case, I am calculating the MPKI and miss rate for LLC, should I use the statistics shown above for L3-cache to obtain them or should I use the statistics of Dram? In this case, sum_of_#missesInL3!=NumDramAccess. so I don't know how to calculate it..

Thanks,

-Rui

[Wim Heirman]

Rui,

You should look at the L3 statistics. DRAM accesses can happen for other reasons, e.g. write-back of dirty data, so it's expected to see more DRAM accesses than LLC misses.

Regards,

Wim

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[rollin...@gmail.com]

Thanks you, Wim. I got it now.
-Rui