Exclusive or Inclusive caches

[Hamid Reza]

Hi group,

As you know caches can be Inclusive, all data in the L1 cache must also be somewhere in the L2 cache (like the AMD Athlon), Exlusive, data is guaranteed to be in at most one of the L1 and L2 caches, never in both. Still other processors (like the Intel Pentium II, III, and 4), do not require that data in the L1 cache also reside in the L2 cache, although it may often do so.

Could you tell me which type of above cache types has been implemented in Sniper?

Thanks

[Wim Heirman]

Hamid,

Sniper implements inclusive caches at all levels.

Regards,

Wim

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[Hamid Reza Khaleghzadeh]

Hi Wim,

As you said, "Sniper implements inclusive caches at all levels". But, I think inclusive cache cannot simulate Clovertown correctly. Consider block1 which is loaded to core0 and core1 (these two cores inside into the same package). So, suppose block1 evicted from L1 cache of core1, and block1 must be evicted from L1 cache of core0, and shared L2, too. This eviction has negative effect on thread affinity and performance. Isn't it?

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Hamid Reza Khaleghzadeh
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[Aiesha Almaslam]

hi Wim
is there any way to implement exclusive property for caches ?
or guide me to what files to modify for this purpose?


thank you alot
Aiesha

[Wim Heirman]

Hi Aiesha,

You can definitely implement exclusive caches, changes will be isolated to cache_cntlr.cc. There are a few cases where the code now assumes inclusion, which you'll have to work around:

- on a cache miss, currently the LLC will be filled with the line (the insertCacheBlock call made from processShRepFromDramDirectory and processExRepFromDramDirectory), and the L1 will make another call through processShmemReqFromPrevCache and expect the line to be in the LLC so it can do the fill using copyDataFromNextLevel. You'll have to make a mechanism here where incoming lines are stored elsewhere for the L1 to access.

- on a dirty eviction from the L1, it will expect to find the line in the next-level cache (in insertCacheBlock, when eviction=true and state=M, m_next_cache_cntlr->writeCacheBlock is called which fails if the line is not in the L2). You can do two things here: install the dirty line in the L2 (potentially evicting another dirty line), or write the line straight through to DRAM (look at the code under the /* Send dirty block to directory */ comment).

- not sure about this last part but there may need to be changes here as well: when an invalidate/writeback request is received from the tag directory (processInvReqFromDramDirectory/processFlushReqFromDramDirectory/processWbReqFromDramDirectory), updateCacheBlock is called on the LLC. In an inclusive hierarchy the LLC can act as a snoop filter, but for an exclusive hierarchy you always need to propagate the invalidation to all cache levels. It looks like the top of updateCacheBlock is doing that anyway (where it iterates over m_prev_cache_cntlrs and calls updateCacheBlock on them), but you'll need to make sure an INV_REP is sent even if the line is not in the LLC>

Regards,

Wim

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